Infineon Technologies Ag

Qimonda Ag

Infineon Technologies North America Corp.

Ralf Klein

Bernd Klehn

Christian Paulus

Thoai-Thai Le

Eckhard Brass

Joachim Schnabel

Wolfgang Hokenmaier

George William Alexander

Herbert Eichfeld

Jong Hoon Oh

Ullrich Menczigar

Margaret Freebern

Donald W Labrecque

Steffen Loeffler

Andrea Zuckerst&auml;tter

Marie-Claire Hoffmann

Dirk Romer

Hermann Fischer

Thomas Schumann

An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal.

Integrated circuit including multiple memory devices

An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array.

Integrated circuit including selectable address and data multiplexing mode

The invention relates to an input circuit for an electronic circuit, for receiving and assessing an input signal and for driving the input signal to a downstream circuit. The input circuit includes a first reception circuit which is configured to receive and drive the input signal and has a first current consumption characteristic, the current consumption of the first reception circuit depending on the input signal to be driven, a second reception circuit which is configured to receive and drive the input signal and has a second current consumption characteristic, the current consumption of the second reception circuit depending on the input signal to be driven, wherein the first reception circuit and the second reception circuit may be activated separately, and a control circuit configured to activate either the first reception circuit or the second reception circuit and to deactivate the respective other reception circuit on the basis of the driven input signal.

Reducing current consumption for input circuit of an electronic circuit

A driver circuit which has one or more driver transistors connected to a load and which further includes at least one circuit block configured to control the voltage on the gate nodes of the one or more driver transistors and which is connected to the latter. The gate source voltage of the one or more driver transistors can be controlled, using an appropriate configuration of the circuit blocks in relation to the circuit, by the application of the current in such a way that the charging/discharging current is approximately sine. The circuit block has a current source that controls the gate voltage on the gate nodes of the one or more driver transistors and the circuit block as an additional first voltage source that provides the operating voltage of the driver circuit, in addition to a second voltage source that provides a control voltage which is used to adapt the driver circuit to different load magnitudes.

Drive circuit

A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element, which in the off state isolates the first reading amplifier from the bit line, is provided. The method comprises: a) turning on the switching element to connect the first reading amplifier to the bit line, b) activating the word line to activate the memory cell for reading, c) activating the first reading amplifier to initiate assessment of the information on the bit line, d) turning off the switching element to isolate the first reading amplifier from the bit line, and e) transferring the information which has been read to a data bus.

Method and circuit for reading a dynamic memory circuit

A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal is synchronized with the read signal, it is possible to provide more time to read data into the buffer. A method of reading data from a memory device couples a synchronization enable signal and an external clock signal to a synchronization circuit. A read signal and an output enable are generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.

Memory device and method of reading data from a memory device

The invention relates to a driver circuit () for integrated circuits comprising at least one input node () for an input signal and at least one output node () for an output signal. One or several, preferably two partial drivers () supply approximately sine-wave shaped current to the load capacity () thereby improving electromagnetic compatibility. A feedback circuit () is also provided. Said feedback circuit consists of one or several evaluation circuits () and one or several feedback capacitors (). The evaluation circuits () are connected to the partial drivers () One feedback capacitor () is respectively arranged between an output node () of the driver circuit () and an input node () of an evaluation circuit (). An evaluation circuit () is provided via the feedback condenser () between an output node () of the driver circuit and an input node (). The edge steepness of the signal i.e. current which is independent of the actual load, can be produced by means of a feedback circuit (). The feedback capacitor () can, for example, be embodied as a non-linear capacitor.

Driver circuit and method for operating a driver circuit

In a scalable driver device having a plurality of driver stages whose outputs are connected to a common terminal contact for providing a common output signal, drive parameters of the driver stages, individually or in groups, are so dimensioned that the difference of the edge rise times and/or fall times of the output signal from one active driver stage to the next driver stage to be activated is substantially equal to the difference of the edge rise times and/or fall times from a next activated driver stage to the one activated after that.

Scalable driver device and related integrated circuit

A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the counter reading is used for regulating the phase or frequency relationship. Trials have shown that the counter reading indicates an operating state in the circuit configuration and therefore represents a simple signal for assessing the operating state of the circuit configuration. Preferably, the counter reading is taken as a basis for adjusting the speed or power of time-critical or performance-critical circuit parts in the circuit configuration so that an operating state with an intermediate switching speed is obtained.

Circuit configuration for processing data, and method for identifying an operating state

The invention relates to an arrangement ( ) and a method for adjusting the slope times of one or more drivers ( ) in such a way that the adjustment is essentially independent of external conditions. The invention also relates to a driver circuit. The arrangement ( ) is provided with a device ( ) for detecting the time history of an output voltage that is output and supplied to a load ( ) by means of the driver/s ( ). The measured time values are converted into an output voltage value in a device ( ) for converting the measured time history of the output voltage. Moreover, a device ( ) for generating a reference voltage value is provided. The device ( ) is connected to a device ( ) for predetermining a desired slope time for the driver/s ( ), whereby the slope time is essentially independent of external conditions. A system pulse can be partitioned into differently long rectangular pulses in the device ( ) in such a way that the user of the arrangement ( ) can select from the group of the rectangular pulses which match certain slope times respectively. The output voltage value and the reference voltage value are compared in a comparing device ( ) that is also connected to the driver/s ( ) in such a way that the driver/s ( ) can be readjusted thereby.

Arrangement and method for adjustment of the slope times for one or more drivers and a driver circuit

A method for driving a plurality of circuit units to be controlled includes applying a control signal to a control signal connection unit and an activation signal to an activation connection unit. A hold signal is the generated on the in response to the activation signal. This hold signal is combined with the control signal to obtain a modified control signal, which is then made available at an output.

Control signal generating device for driving a plurality of circuit units

An output driver circuit includes a delay device disposed between a signal input and a driver device. The input signal to the driver device can be delayed by a predetermined value with the delay device. The signal amplitude of the output signal from the driver device is compared, in a comparison device, with the signal amplitude of a reference signal at a predetermined time. The time delay for the input signal to the driver device is then set on the basis of the comparison result. A method for adjusting a driver device is also provided.

Output driver circuit and method for adjusting a driver device

A delay adjustment circuit for decreasing a phase shift between a system clock and a feedback clock from a semiconductor's internal clock. The circuit includes a difference-pulse generator that provides an interim clock 180 degrees out of phase with the feedback clock when the feedback clock is leading the system clock, and equal to the feedback clock otherwise. The difference-pulse generator also provides a difference-pulse signal that is at logic high for a period of time by which the system clock and an inversion of the interim clock are phase shifted. The circuit also includes a delay control unit and a delay unit which delay the interim clock by the period of time. The resulting delayed interim clock, which is 180 degrees out of phase with the system clock, is inverted to provide an internal clock in phase with the system clock.

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Deidesheim, Germany

Ralf Klein