Lucent Technologies Inc.

Agere Systems Inc.

Alcatel-lucent USA Inc.

Alcatel Lucent

Ralf Dohmen

Adriaan J De Lind Van Wijngaarden

Meng-Lin Yu

Leilei Song

Timo Frithjof Schuering

Raul Benet Ballester

Swen Wunderlich

Bernd Dotterweich

Mark A Bordogna

Herbert Haunstein

Konrad Sticht

Miguel Robledo

Christoph Schulien

Achim Herzberger

Georg Roell

Wolfram Sturm

A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

High speed syndrome-based FEC encoder and system using same

A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats, including the Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats, perform a search for both a frame alignment sequence (FAS) and the inverted FAS and determine the polarity of the received digital stream.

Method and apparatus for providing frame synchronization in a digital communication system that supports multiple modulation formats

A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats perform a search for a differential frame alignment sequence (FAS) to frame-align the received digital stream and determine the polarity of the stream. Embodiments of the invention are compatible with Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats.

Method and apparatus for multi-modulation frame synchronization in a digital communication system

Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.

Noisy channel emulator for high speed data

A method of adjusting equalization parameters in a receiver wherein a bit error rate (BER) in a data stream is measured from the number of corrected bits in data blocks which have an information section and an error correction section. A predetermined equalization parameter is changed, and the bit error rate (BER) after change is again measured to find out how to change the predetermined equalization parameter until an optimum is reached. When adjusting the threshold value of the receiver, the history of occurring bits preceding the actual sampled bit is taken into consideration in that the amount and direction of adjustment is derived from a look-up table.

Adjustment for equalization parameters in receivers

High speed syndrome-based FEC encoder and decoder and system using same

Memory requirements and processing delays associated with the application of forward error correction in high speed optical transmissions are substantially reduced by mapping a forward error correction code on a row-by-row basis into unused overhead bytes in a high bit rate signal frame. By applying the forward error correction code to an entire row of the signal frame on a row by row basis, approximately one row needs to be stored at a time thereby reducing the total memory requirements for forward error correction processing. Using SONET as an exemplary application, approximately {fraction (1/9)}th of the entire SONET frame (e.g., one of nine rows) needs to be buffered for forward error correction processing. In an illustrative embodiment, four forward error correction (FEC) blocks are provided for each row for a total of 36 FEC blocks for a frame. Each FEC block comprises four bytes of correction bits for a total of 32 correction bits. These 32 correction bits are mapped to unused overhead and are used for correcting errors in one block of one row of a signal frame, wherein one block covers &frac14;th of the row. Other unused overhead bytes in the row can be used to carry error detection codes for detecting multiple errors in a row to determine when forward error correction should be disabled. For example, if a single bit error correcting code is employed, then error correction can be disabled to avoid false corrections if more than one error is detected.

Forward error correction for high speed optical transmission systems

Growing community of inventors

Nuremberg, Germany

Ralf Dohmen