Thomson Licensing

Ralf-Detlef Schaefer

Axel Kochale

Klaus Gaedke

Michael Drexler

Marten Kabutz

Friedrich Timmermann

Herbert Schütze

A bit clock recovery apparatus for digital storage readout employing sync frames, where an oversampled readout signal is stored in memory, sync patterns are located in the signal using DSP means, distances of consecutive sync pattern locations are calculated, and bit clock is recovered from these distances and the knowledge about the data framing structure.

DSP-based data recovery

An electronic circuit includes a first and a second PLL stage (PLL, PLL) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input signal (IN). When in parallel, only the second PLL circuit (PLL) is actively supplying a clock signal to the output of the electronic circuit. The first PLL circuit (PLL) continues trying to lock onto the input signal (IN). A lock detector (LD) monitors the locking status of the first PLL circuit (PLL) to the input signal (IN) and, upon locking, sets switches (S, S) to couple the output of the first PLL circuit (PLL) to the input of the second PLL circuit (PLL), and to couple the output of the second PLL circuit (PLL) to the input of the first PLL circuit (PLL).

Switchable PLL circuit

Growing community of inventors

Celle, Germany

Ralf-Detlef Schaefer