Elmos Semiconductor Ag

Ralf Bornefeld

Andreas Gehrmann

The MOS transistor with high voltage sustaining capability and low closing resistance comprises a substrate doped with charge carriers of a first line type. In the substrate drain and source regions are configured doped with charge carriers of a second line type opposed to the first line type. Further, the MOS transistor is provided with a gate electrode arranged in the region between the drain and the source regions on the substrate and comprising a drain-side end region. A drain extension region is doped with charge carriers of the second line type, connected with the drain region and extends to below the drain-side end of the gate electrode. The drain extension region is produced by an ion implantation process comprising at least a first implantation step. The drain extension region comprises in its region near the top side and facing the top side of the substrate a lower doping material concentration than in its region below the region near the top side.

MOS transistor with high voltage sustaining capability and low on-state resistance

In a method for producing an integrated circuit using a CMOS process, in particular a HV CMOS process, components are formed within troughs of different depths and of a first conductivity type, in particular N-type troughs, which are formed in a substrate layer of a second conductivity type opposite to the first conductivity type, in particular a P-type substrate. Further, a SOI wafer substrate is used that comprises a top substrate layer for forming the CMOS components, a lateral insulation layer provided beneath the substrate layer, and a support layer arranged beneath the insulation layer. The top substrate layer has a thickness less than or equal to the greatest trough depth of the CMOS process. The top substrate layer is provided with trench insulation areas down to the subjacent lateral insulation layer, and components are formed within the areas of the silicon layer intermediate the trench insulation areas using the CMOS process, wherein the troughs of the greatest depth (high-voltage N-type trough) extend to the insulation layer and fill the respective area entirely, and wherein components are integrated directly in the troughs of the greatest depth (high-voltage N-type trough), whereas, for components requiring a lesser trough depth, the troughs (logic N-type trough) surrounding these components are provided in troughs of the greatest depth (high-voltage N-type trough).

Growing community of inventors

Schalksmuehle, Germany

Ralf Bornefeld