Infineon Technologies Ag

Siemens Aktiengesellschaft

Ralf Arnold

Wolfgang Anton Spirkl

Heinz Mattes

Christian Siemers

Helge Kleve

Gerd Frankowsky

Peter Ossimitz

Christian Robert Mueller

Siegmar Köppe

Hans-Dieter Oberle

Ernst-Josef Kock

Martin Glas

Volker Schöber

Klaus Standner

Hermann Obermeir

Matthias Heinitz

Thorsten Klose

Lukas Niedergriese

A method for determining an emission coefficient of a device under test (DUT) using a test circuit comprises coupling a parameter measurement circuit associated with the test circuit to an input pin associated with the DUT, wherein the input pin is coupled to a diode element within the DUT and performing voltage and current measurements associated with the input pin using the parameter measurement circuit. In some embodiments, the method further comprises determining a plurality of contact resistance values respectively based on the voltage and current measurements and an emission coefficient estimate using a contact resistance estimation circuit; and determining an emission coefficient associated with the DUT based on the determined plurality of contact resistance values using an emission coefficient determination circuit.

High accurate contact resistance measurement method using one or more diodes

A signal generating circuit, may include an analog signal generator having an output and a control input, the analog signal generator configured to generate at the output an analog output signal in accordance with a timing parameter; an analog-to-digital converter (ADC) having an input and an output, the input coupled to the output of the analog signal generator, the ADC configured to generate a sequence of signal values dependent on the analog signal received at the input; a configurable digital signal generator comprising an output and a control input, the digital signal generator configured to generate a digital output signal in accordance with signal parameters received at the control input; and a control circuit having an input coupled to the output of the ADC.

Signal generating circuit

An electronic element, test system and method of testing an electronic circuit are provided. The electronic circuit has input and output terminals. The input terminals receive a test signal sequence to test the electronic circuit. Actual value signals of a 3-value logic of the electronic circuit are provided at the output terminals in response to the test signal sequence. A comparator circuit has first and second input terminals and an output terminal. Each of the output terminals of the electronic circuit are coupled to a first input terminal. The second input terminals receive desired value signals. The comparator circuit compares the actual value signals with the desired value signals and provides the comparison to the output terminal of the comparator circuit.

Electronic element comprising an electronic circuit which is to be tested and test system arrangement which is used to test the electronic element

An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the protective circuit; and an additional circuit including a first input coupled to the signal terminal via the protective circuit, and an output that provides a test value for operation of the input and output circuit.

Input and output circuit of an integrated circuit and a method for testing the same

In order to test digital modules with functional elements, these are divided into test units () which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (), and the test responses resulting from this are evaluated at the outputs of the test unit (). The effect is then encountered that changes at each of the inputs of a test unit () do not all affect a particular output of this test unit (). For every output of the test unit (), it is possible to define a cone () whose apex is formed by the particular output of the test unit () and whose base comprises the inputs of the test unit () where, and only where, changes affect the particular output. According to the invention, the test pattern to be applied to the inputs of the test unit () is constructed of sub-patterns, whose length is in particular &#x2266; the number of inputs of the test unit () that are contained in the base of a cone (). Owing to their shorter length, all possible combinations can be used for selecting the sub-patterns, so that a comprehensive function test of the test unit () can be carried out rapidly and with little outlay. In a digital module, this test function may in particular be implemented by a self-test unit () which can switch over the rest of the digital module into a test mode, generates the test patterns on the basis of sub-patterns, loads them into a test-pattern output register () for application to a test unit () and can evaluate the test response subsequently found at the outputs of the test unit () by means of an evaluation unit (), or read it in for evaluation.

System for testing digital components

A test apparatus includes a signal source that generates a radio-frequency test signal and is connected to the input connection of an arrangement. The arrangement simultaneously supplies an electrical radio-frequency signal to a plurality of receivers and via a plurality of distribution lines. Each distribution line includes an end with an output connection that applies the power-matched test signal to a respective external component.

Test apparatus with low-reflection signal distribution

Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.

Semiconductor circuit device and a system for testing a semiconductor apparatus

Transfer switching devices, which supplement unidirectional input switching arrangements or pad circuits are employed to route an internal test signal to the input of an input driver in the unidirectional input switching arrangement and to couple the internal test signal to an internal switching logic unit. The transfer switching devices are controlled via a multiplexer unit, which can be programmed directly using boundary scan registers. The present invention allows all unidirectional pad circuits or input drivers to be tested in the course of a reduced I/O test method for semiconductor circuits, in which testing internal circuits in the semiconductor circuit involves only a subset of the signal connections associated with the input drivers being coupled to a test apparatus.

Input switching arrangement for a semiconductor circuit and test method for unidirectional input drivers in semiconductor circuits

The configurable hardware block is designed to read data stored in a memory according to its configuration, to process the read-out data arithmetically and/or logically and to write the data representing the result of the processing into the memory. The hardware block is capable of interacting with external hardware, thereby providing a flexible and universally applicable hardware block.

Configurable processing block capable of interacting with external hardware

A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type of subunit of a configurable hardware block, the given type of subunit being required for executing a respective command, selecting, if available, a subunit of the given type of subunit, configuring configurable connections provided around the subunit selected in the selecting step, if the subunit of the given type of subunit is found in the selecting step, and ascertaining configuration data with the step of implementing the commands and/or command sequences. The configurable hardware block is configured by using the configuration data.

Method for configuring a configurable hardware block by configuring configurable connections provided around a given type of subunit

A method described is distinguished by the fact that an external test device brings about the execution, in a program-controlled unit, of a program that initiates, performs or supports the testing of the program-controlled unit. As a result, program-controlled units can be rapidly and reliably tested under all circumstances with minimal outlay.

Growing community of inventors

Poing, Germany

Ralf Arnold