Texas Instruments Corporation

Rakul Viswanath

Nagesh Surendranath

Sandeep Kesrimal Oswal

Ratna Kumar Venkata Parupudi

Rahul Anand Sharma

Eduardo Bartolome

Goli Sravana Kumar

Prasanth K

Sravana Kumar Goli

Rajashekar Goroju

Dileepkumar Ramesh Bhat

Sachin Aithal

In a described example, an apparatus includes: a photon detector array with a first signal output pad coupled to a photon detector array pixel; a die carrier comprising a readout integrated circuit (ROIC) die and a conductor layer having conductors that couple a first signal input pad on the conductor layer to an input signal lead of the ROIC die; and the first signal output pad coupled to the first signal input pad.

Photon detector array assembly

An example apparatus includes: controller circuitry configured to: provide switch signals to capacitive digital to analog converter (C-DAC) circuitry, the C-DAC circuitry including switches; configuring the switches into a third configuration begin an Auto Zero (AZ) phase with a third switch in a closed state; configuring the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to a first configuration; configuring the switches into a fifth configuration to repeat the transition of a first switch and a second switch to the open state corresponding to a second configuration; configuring the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to a second configuration; and performing an AZ decision with the switches in the sixth configuration.

Methods and apparatus to capture switch charge injections and comparator kickback effects

An analog front-end circuit includes an array of pixel circuits. Each pixel circuit includes an event counter and a power consumption circuit. The event counter is configured to count photons incident at the pixel circuit. The power compensation circuit includes an event rate circuit and a current sink circuit. The event rate circuit is configured to determine a rate of photon detection events at the pixel circuit. The current sink circuit is configured to pass a compensation current selected based on the rate of photon detection events at the pixel circuit.

Photon counting analog front end with load balancing

In described examples, a charge sensitive amplifier (CSA) generates an integrated signal in response to a current signal. A high pass filter is coupled to the CSA and receives the integrated signal and an inverse of an event signal, the high pass filter generates a coarse signal. An active comparator is coupled to the high pass filter and receives the coarse signal and a primary reference voltage signal, the active comparator generates the event signal.

Dynamic noise shaping in a photon counting system

A circuit for use in a system that includes a detector, wherein the circuit comprises an input terminal to receive a detector signal from the detector external to the circuit, the detector signal to include an error charge corresponding to a leakage current. The circuit further comprises an amplifier coupled to the input terminal to receive input signals corresponding to the detector signal, including the error charge applied to an input of the amplifier. The circuit further comprises a feedback path coupled across the amplifier, wherein the feedback path comprises a first switch coupled across a leakage resistor and to a leakage capacitor for discharging a feedback compensation charge from the leakage capacitor and onto the input of the amplifier to substantially cancel the error charge.

Leakage compensation for a detector

A dark current compensation circuit comprises a first comparator having inputs for a detection signal and a first voltage, and a second comparator having inputs for the detection signal and a second voltage. The dark current compensation circuit also comprises a controller coupled to the first and second comparators, which has an input for an event signal. An adjustable current source is coupled to the controller and configured to generate a compensation current. The controller adjusts a value of the compensation current based on the first and second comparator outputs and maintains a constant value in response to the event signal indicating photons incident on a photon detector. In some implementations, the dark current compensation circuit further comprises an analog sub-circuit coupled to the adjustable current source and configured to receive the detection signal. The analog sub-circuit generates an analog compensation current in response to the detection signal.

Hybrid leakage-compensation scheme for improved correction range

A photon counting system includes a photon sensor, a charge-sensitive amplifier (CSA) and an analog-to-digital converter (ADC). The CSA is configured to convert photon energy detected by the photon sensor to voltage pulses. The ADC is configured to digitize the voltage pulses generated by the CSA. The ADC includes successive approximation circuitry. The successive approximation circuitry includes an N-bit digital-to-analog converter (DAC), an N-bit successive approximation register (SAR), a plurality of N-bit registers, and a multiplexer configured to selectively route outputs of the SAR and outputs of the N-bit registers to the DAC for conversion to an analog signal.

Configurable analog-to-digital converter and processing for photon counting

A circuit includes a charge sensitive amplifier (CSA) that includes an input to receive current from a photon sensor and generates an output signal that represents photons received by the sensor and dark current of the sensor. A control circuit generates a compensation signal to offset the dark current from the photon sensor at the input of the CSA. The control circuit couples feedback from the CSA to enable the compensation signal if the photon current received from the sensor is below a predetermined threshold. The control circuit decouples the feedback from the CSA to disable the compensation signal if the photon current received from the sensor is above the predetermined threshold.

Dark current compensation for photon counting circuit

The disclosure provides a circuit that includes a charge sensitive amplifier (CSA) that generates an integrated signal in response to a current signal. An active comparator is coupled to the CSA. The active comparator receives the integrated signal and a primary reference voltage signal, and generates an event detect signal. A first delay element is coupled to the active comparator and provides a fixed delay to the event detect signal to generate a convert signal. A discriminator system is coupled to the CSA. The discriminator system samples the integrated signal when activated by the convert signal.

Low power photon counting system

A photon counting system includes a photon sensor and pixel circuitry. The pixel circuitry includes a charge sensitive amplifier (CSA), an analog to digital converter (ADC), an event detector, and a coincidence detector. The CSA is configured to convert photon energy detected by the photon sensor to a voltage pulse. The ADC is coupled to an output of the CSA. The ADC is configured to digitize the voltage pulses generated by the CSA. The event detector is configured to determine whether output voltage of the CSA exceeds an event threshold voltage, and to trigger the ADC to digitize the output voltage based on the output voltage exceeding the event threshold voltage. The coincidence detector is configured to determine whether the output voltage of the CSA exceeds a coincidence threshold voltage, and to trigger the ADC to digitize the output voltage based on the output voltage exceeding the coincidence threshold voltage.

Photon counting with coincidence detection

A bootstrap circuit for a sampling transistor. A circuit includes a MOS transistor having a source terminal coupled to an input for receiving an input voltage; an output at a drain terminal of the MOS transistor coupled to one plate of a sampling capacitor; a first switch coupling the input voltage to a gate terminal of the MOS transistor responsive to an initial phase control signal; a bootstrap capacitor having a top plate coupled to the gate terminal of the MOS transistor and coupled to the first switch; a second switch coupling a bottom plate of the bootstrap capacitor to a first low voltage supply responsive to the initial phase control signal; a third switch coupling the bottom plate of the bootstrap capacitor to a positive voltage supply greater than the first low voltage supply responsive to a first phase periodic control signal. Additional circuits and systems are disclosed.

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Chennai, India

Rakul Viswanath