Iii Holdings 2, LLC

Bluerisc, Inc.

Google Inc.

Other

University of Massachusetts

Raksit Ashok

Dong Hyuk Woo

Saurabh Chheda

Kristopher Carver

Robert Hundt

Xinliang David Li

Csaba Andras Moritz

Israel Koren

Mani Krishna

Osman Sabri Unsal

Arun Chauhan

A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.

Energy-focused compiler-assisted branch prediction

A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.

Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control

A method, for use in a processor context, wherein instructions in a program executable are encoded with plural instruction set encodings. A method wherein a control instruction encoded with an instruction set encoding contains information about decoding of an instruction that is encoded with another instruction set encoding scheme. A method wherein instruction set encodings are randomly generated at compile time. A processor framework wherein an instruction is decoded during execution with the help of information provided by a previously decoded control instruction.

Security of program executables and microprocessors based on compiler-architecture interaction

A method includes generating a first executable program module based on source code modules and collecting profile information for the source code modules by executing the first executable program module. The profile information includes information pertaining to invocation of procedures in the first executable program module. The method further includes determining module grouping information for the source code modules based on procedure invocation patterns in the profile information and according to one or more inter-procedural optimization (IPO) heuristics. The method includes performing IPO based on the module grouping information to generate object code modules and generating a second executable program module based on the plurality of object code modules.

Feedback-directed inter-procedural optimization

Methods, systems, and apparatus, including computer program products, for inter-procedural optimization, are disclosed. In one aspect, a first executable program module is generated based on a plurality of source code modules. Profile information is collected for the plurality of source code modules by executing the first executable program module. Inter-procedural analysis for the plurality of source code modules is performed during execution of the first executable program module. The inter-procedural analysis is based on the collected profile information. IPO is performed based on the results from the inter-procedural analysis to generate a plurality of object code modules. A second executable program module is generated based on the plurality of object code modules.

A processor framework includes a compiler to add control information to an instruction sequence at compile time. The control information is added in the instruction sequence prior to a control-flow changing instruction. Microarchitecture is configured to use the control information at runtime to predict an outcome of the control-flow changing instruction prior to fetching the control-flow changing instruction.

A method, for use in a processor, includes mapping a first data access having less than a predetermined memory footprint to a first memory area, and mapping a second data access having greater than the predetermined memory footprint to a second memory area. The method may also include compiling computer code, inserting annotations into an intermediate representation of the computer code generated during compiling, propagating the annotations from the intermediate representation to a low-level representation of the computer code generated during compiling, and inserting instructions into the low-level representation, the instructions controlling mapping of the first data and the second data.

Growing community of inventors

Sunnyvale, CA, United States of America

Raksit Ashok