Samsung Electronics Co., Ltd.

Rakhwan Kim

Eun-Ji Jung

Eui Bok Lee

Woojin Jang

Jongjin Lee

Wonhyuk Hong

Wandon Kim

Dongsoo Lee

Jaeyeol Song

Seungha Oh

Daeyong Kim

Minjung Park

Sunyoung Noh

Seungyong Yoo

Won Kyu Han

Myeongsoo Lee

Kyungwook Kim

Dongwoo Kim

Jinnam Kim

Hoonjoo Na

Dohyun Lee

Jae-Jung Kim

Hyunbae Lee

Kichul Park

Seungseok Ha

Jongchan Shin

Ki Chul Park

Euibok Lee

Minjoo Lee

Hanmin Jang

KyoungWoo Lee

Anthony Dongick Lee

Juyoung Jung

Seowoo Nam

Sangcheol Na

Yoonsuk Kim

Doohwan Park

Eunji Jung

Sungyu Choi

Seongheum Choi

Chanhyeong Lee

A semiconductor device may include a channel pattern stacked on a substrate and a gate electrode on the substrate. The channel pattern includes semiconductor patterns. The gate electrode extends to cross the channel pattern. The gate electrode may include dielectric layers, first work function adjusting patterns, and second work function adjusting patterns. The dielectric layers may enclose the semiconductor patterns, respectively. The first work function adjusting patterns may enclose the dielectric layers, respectively, and the second work function adjusting patterns may enclose the first work function adjusting patterns, respectively. The first work function adjusting patterns may be formed of an aluminum-containing material, and each corresponding one of the first work function adjusting patterns may be in contact with a corresponding one of the second work function adjusting patterns enclosing the corresponding one of the first work function adjusting patterns.

Semiconductor device and method of fabricating the same

A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.

Semiconductor devices

Disclosed is a semiconductor device including a substrate, a first interlayer dielectric layer on the substrate, a plurality of first vias in the first interlayer dielectric layer, a second interlayer dielectric layer on the first interlayer dielectric layer, and a first power line and a first lower line in the second interlayer dielectric layer that are electrically connected to respective ones of the first vias. A first width in a first direction of the first power line is greater than a second width in the first direction of the first lower line. The first power line includes a first metallic material. The first lower line includes a second metallic material. The first vias includes a third metallic material. The first, second, and third metallic materials are different from each other.

Semiconductor device

A semiconductor device includes a substrate. A wiring layer is over the substrate. A first via structure directly contacts a lower portion of the wiring layer. A second via structure directly contacts an upper portion of the wiring layer. The first via structure generates first stress in the wiring layer. The second via structure generates second stress in the wiring layer. The second stress is of an opposite type to the first stress. The first stress and the second stress compensate for each other in the wiring layer.

Semiconductor device including via structure

A semiconductor device includes a front-end-of-line (FEOL) layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.

A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

Semiconductor device having interconnection lines with different linewidths and metal patterns

A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

Semiconductor devices and methods of fabricating the same

An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

Integrated circuit devices having improved contact plug structures therein

A semiconductor device includes an active region extending in a first direction on a substrate; a gate structure extending in a second direction on the substrate, intersecting the active region, and including a gate electrode, source/drain region disposed on the active region on at least one side of the gate structure, a first contact structure connected to the source/drain region; a first gate contact structure disposed on and connected to the gate electrode; a second contact structure disposed on and connected to the first contact structure; and a second gate contact structure disposed on and connected to the first gate contact structure. The second contact structure and/or the second gate contact structure may include an upper metal layer and a metal liner covering a lower surface and side surfaces of the upper metal layer. An external surface of the metal liner may have surface roughness.

The present disclosure provides a semiconductor device. The semiconductor device includes an active region, a plurality of channel layers, gate electrodes, a source/drain region, and a contact structure. The active region is disposed on a substrate and extends in a first direction. The plurality of channel layers are disposed on the active region to be spaced apart from each other vertically. The gate electrodes are disposed on the substrate, intersecting the active region and the plurality of channel layers, extending in a third direction, and surrounding the plurality of channel layers. The source/drain region is disposed on the active region on at least one side of the gate electrodes, and contacting the plurality of channel layers. The contact structure is disposed between the gate electrodes, extending in the second direction, and contacting the source/drain region.

Multi-bridge channel field effect transistor with recessed source/drain

An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

Integrated circuits and method of manufacturing the same

Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.

Semiconductor devices and methods for manufacturing the same

Semiconductor devices including via structures having a via portion and a barrier portion

Growing community of inventors

Suwon-si, South Korea

Rakhwan Kim