Qualcomm Incorporated

Rakesh Vattikonda

Changho Jung

Nishith Nitin Desai

Sei Seung Yoon

De Lu

Samrat Sinharoy

Esin Terzioglu

Ramaprasath Vilangudipitchai

Venkat Narayanan

Rui Chen

Ravindraraj Ramaraju

Chulmin Jung

Frank Guo

Bo Pang

Nishith Desai

In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.

Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors

In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

High speed voltage level shifter

In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

Apparatus for design for testability of multiport register arrays

In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

Apparatus and method for writing data to memory array circuits

A level-shifter is provided with PMOS stacks that are selectively weakened or strengthened depending upon the binary state of an input signal.

Wide-range level-shifter

Various apparatuses and methods are disclosed. The system describes a pulse generator comprising a first stage configured to be powered by a first voltage; and a second stage configured to be powered by a second voltage different from the first voltage, wherein the second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage.

Pulse generation in dual supply systems

A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Static NAND cell for ternary content addressable memory (TCAM)

A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMto the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP&#x2267;VddM&#x3e;VddM.

Write driver for write assistance in memory device

Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power. The write driver circuit shifts or adjusts voltage levels between a first voltage domain to a second voltage domain. In one example, the write driver circuit is coupled to a global write bitline and a local write bitline that is coupled to one or more bitcells (of SRAM memory). The write driver circuit converts a first voltage level at the global write bitline to a second voltage level at the local write bitline during a write operation.

High-speed memory write driver circuit with voltage level shifting features

A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.

Wide range multiport bitcell

A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.

Hybrid ternary content addressable memory

A method within a ternary content addressable memory (TCAM) includes receiving a match line output from a previous TCAM stage at a gate of a pull-up transistor of a current TCAM stage and at a gate of a pull-down transistor of the current TCAM stage. The method sets a match line bar at the current TCAM stage to a low value, via the pull-down transistor, when the match line output from the previous TCAM stage indicates a mismatch. The method also sets the match line bar at the current TCAM stage to a high value, via the pull-up transistor, when the match line output from the previous TCAM stage indicates a match.

Growing community of inventors

San Diego, CA, United States of America

Rakesh Vattikonda