Arm Limited

Rakesh Shaji Lal

Abhishek Raja

Michael Filippo

Miles Robert Dooley

Glen Andrew Harris

Huzefa Moiz Sanjeliwala

Jason Lee Setter

Vasu Kudaravalli

A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, following instructions that appear after the status updating instruction in the instruction stream.

Speculatively executing instructions that follow a status updating instruction

An apparatus and method are provided for efficient utilisation of an address translation cache. The apparatus has an address translation cache with a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Each entry identifies whether the address translation data stored therein is coalesced or non-coalesced address translation data, and also identifies a page size for a page within the memory system that is associated with that address translation data. Control circuitry is responsive to a virtual address, to perform a lookup operation within the address translation cache to produce, for each page size supported by the address translation cache, a hit indication to indicate whether a hit has been detected for an entry storing address translation data of the associated page size. The control circuitry is further arranged to determine, from at least each hit indication for a page size that is able to be associated with coalesced address translation data, a coalesced multi-hit indication which is set when a hit is detected for both an entry containing coalesced address translation data and for an entry containing non-coalesced address translation data. The control circuitry is then arranged, when the lookup operation has completed, to determine whether multiple hits have been detected, and in that instance to reference the coalesced multi-hit indication to determine whether multiple hits have resulted from both coalesced address translation data and non-coalesced address translation data in the address translation cache. This provides an efficient and precise mechanism for distinguishing between multiple hits caused by hardware coalescing and multiple hits caused by software induced issues.

Apparatus and method for efficient utilisation of an address translation cache

A computer implemented method, and an apparatus, are provided for performing a scalability check on a Hardware Description Language (HDL) representation of a circuit. The HDL representation identifies a plurality of sink signals, where each sink signal is arranged to take a result value computed by performing an operation using as input one or more driver signals. The method comprises creating within a storage a mapping table to map drivers signals to sink signals, where each entry identifies a sink signal and an associated sink width indication, identifies each driver signal used in the computation of the result value for that sink signal along with an associated driver width indication for each driver signal, and an operation type indication for the operation used to compute the result value for the sink signal. A scalability check operation is then executed on processing circuitry for one or more selected entries in the mapping table that have at least one of the sink and driver width indications specified with reference to at least one parameter. The scalability check operation comprises determining, using the operation type indication and the driver width indication for each driver signal, a driver signal identifying an expected width for the sink signal, and determining using the sink width indication a sink formula to identify the width of the sink signal. The sink formula and the driver formula are then evaluated to determine whether the presence of the at least one parameter gives rise to a scalability issue. A result file is then output identifying each sink signal that has been detected to have a scalability issue.

Apparatus and method for performing a scalability check on a hardware description language representation of a circuit

Growing community of inventors

Austin, TX, United States of America

Rakesh Shaji Lal