Meta Platforms Technologies, LLC

Intel Corporation

Rakesh Ranjan

Brian Keith Cabral

Ganesh Venkatesh

Samuel Alan Johnson

Albert Parra Pozo

Amit Kumar

Michael Alexander Snower

Yash Patel

Joseph Virskus

Kai Li

Shen-Chi Chen

Wei Ye

Sebastian Winkel

Arun Raman

Jaroslaw Topp

Ulrich Bretthauer

Gregor Stellpflug

Rainer Theur

A holographic calling system can capture and encode holographic data at a sender-side of a holographic calling pipeline and decode and present the holographic data as a 3D representation of a sender at a receiver-side of the holographic calling pipeline. The holographic calling pipeline can include stages to capture audio, color images, and depth images; densify the depth images to have a depth value for each pixel while generating parts masks and a body model; use the masks to segment the images into parts needed for hologram generation; convert depth images into a 3D mesh; paint the 3D mesh with color data; perform torso disocclusion; perform face reconstruction; and perform audio synchronization. In various implementations, different of these stages can be performed sender-side or receiver side. The holographic calling pipeline also includes sender-side compression, transmission over a communication channel, and receiver-side decompression and hologram output.

Holographic calling for artificial reality

A system includes a processor with a front end to receive an instruction stream reordered by a software scheduler and including a plurality of memory operations and alias information indicating how a given memory operation may be evaluated. Furthermore, the processor includes a hardware scheduler to reorder, in hardware, the instruction stream for out-of-order execution. In addition, the processor includes a calculation module to determine, for a given memory operation and based upon the alias information, a checking range of memory atoms subsequent to the given memory operation and a virtual order of the memory operation. The virtual order indicates an original ordering of the instructions. The processor also includes an alias unit to reorder the instruction stream, determine whether the hardware reordering caused an error, and determine whether the software reordering caused an error based upon the checking range and the virtual order.

Instruction and logic for memory disambiguation in an out-of-order processor

Growing community of inventors

Mountain View, CA, United States of America

Rakesh Ranjan