Ampere Computing LLC

Rakesh Kumar

Nagi Aboulenein

Massimo Sutera

Harb Abdulhamid

Sandeep Brahmadathan

Kha Hong Nguyen

Kha Minh Huynh

Anil Kumar Handenahalli Rajanna

Apparatus and methods for extending functionality of memory controllers using a loopback mode for testing are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit configured to receive a memory write request that is directed to and received by a memory controller. The memory access intercept circuit transmits proxy write data to the memory controller, and intercepts write data directed to the memory controller for the memory write request. The memory access intercept circuit stores the write data in a write data buffer, and, upon intercepting the proxy write data from the memory controller directed to a physical (PHY) interface circuit, retrieves the write data from the write data buffer and transmits the write data to the PHY interface circuit. The memory access intercept circuit subsequently receives, from the PHY interface circuit, loopback data, and stores the loopback data in a read data buffer.

Extending functionality of memory controllers using a loopback mode for testing in a processor-based device

A system and method are provided that enables a processor to undergo a functional test of its circuits prior to attachment to a semiconductor package and prior to use in a computing platform. The method of testing chips includes attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions into a memory of the non-packaged semiconductor circuit, and operating the non-packaged semiconductor circuit in a test boot mode and executing the computer instructions in that mode. The operation logs one or more events of the execution of the instructions in the test boot mode and transmits the logs of the one or more events from the non-packaged semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver/transmitter (UART) interface.

Method and system for testing semiconductor circuits

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Cupertino, CA, United States of America

Rakesh Kumar