Shaoxing Yuanfang Semiconductor Co., Ltd.

Qualcomm Incorporated

Rakesh Kumar Gupta

Ankit Seedher

Raja Prabhu J

Srinath Sridharan

Nitesh Naidu

Shivam Agrawal

Christophe Avoinne

Jeevabharathi G

Purva Choudhary

Laurent Rene Moll

Philippe Boucard

Jean-Jacques Lecler

Subbarao Palacharla

Alain Artieri

Shyamkumar Thoziyoor

Samir Vijay Ginde

Kedar Bhole

Luc Montperrus

Sparsh Singhai

Gopi Tummala

Syed Minhaj Hassan

Luigi Vinci

Anurag Pulincherry

Shuvadeep Mitra

Carlo Spitale

Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable

An integrated circuit (IC) includes input/output (I/O) ports, each operating using one of a pair of unequal power supplies during normal operation of the IC. A lower supply of the pair of unequal power supplies is required to be used as the power supply for the I/O port when a first input signal to the IC is received from an external source on a first I/O port of the I/O ports. The voltage range of the logic excursions of the first input signal is greater than the range from a magnitude of the lower supply to a constant reference potential. A regulation loop derives a derived lower supply having a magnitude equaling that of the lower supply from the higher supply of the pair of unequal power supplies, and applies the derived lower supply on a power supply node of the first I/O port.

Preventing reverse-current flow when an integrated circuit operates using power supplies of different magnitudes

A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.

Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock

Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.

Dram-aware caching

Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

Coherent interconnect power reduction using hardware controlled split snoop directories

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Bengaluru, India

Rakesh Kumar Gupta