Cirrus Logic Inc.

Rakesh Kumar Bindlish

Vlad Bril

Alexander Julian Eglit

Sridhar Kotha

Robin Sungsoo Han

Ken Fuiks

Dwarka Partani

Chester F Bassetti, Jr

Sagar Waman Kenkare

Chin-Hsian Chang

Vald Bril

A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data 'tag' (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g., LCD and CRT) are provided to temporarily store video data. FIFO pointers are fed back to a sequence controller to drive data read cycles from display memory. The use of tags and FIFO pointer feedback allows two video displays to be driven at different data rates, allowing for independent resolution and refresh rates in each display.

Dual displays having independent resolutions and refresh rates

The present invention allows a single display controller design to be used in multiple markets by providing an additional stand-alone circuit which converts conventional analog CRT display signals to digital flat panel display or other digital display signals. A single VGA CRT controller may be implemented in both desktop and portable (e.g., laptop) markets thereby reducing the cost of the display controller through the economies of scale. For a laptop or other digital display markets, the apparatus of the present invention may be applied to a conventional analog CRT controller to convert analog CRT signals to digital laptop signals to generate a display on a flat panel display or other digital device. In addition, the apparatus of the present invention may be incorporated into a stand-alone flat panel display intended for use as a replacement for conventional CRT monitors. The apparatus of the present invention accepts a conventional analog CRT input and outputs digital flat panel display signals. When packaged with a flat panel display intended for the desktop PC market, the present invention provides an overall apparatus which is plug-in compatible with prior art analog VGA controllers. The apparatus of the present invention may also incorporate flat panel protection circuitry to prevent damage to a flat panel display during testing or the like. In addition, the present invention further encompasses an apparatus for providing flat panel protection in a stand-alone circuit.

CRT to FPD conversion/protection apparatus and method

Motion video may be imported into a personal or portable computer through an I/O port having a limited data bandwidth, such as a PCMCIA interface. Motion video data is compressed by sub-sampling both luminance and chrominance difference data for different sized groups of pixels. The compression apparatus may be formed on a PCMCIA card which interfaces with a personal or portable computer. Motion video data, compressed by as much as 5:1 or 6:1, is transferred through the PCMCIA card to a host computer. The host computer may serialize the compressed data and store the data in serialized compressed format in a video memory of a video controller. The video controller is provided with decompression circuitry to decompress the motion video data into luminance and chrominance difference data. The luminance and chrominance difference data is converted into RGB data and displayed in a video display.

PCMCIA video card

The display controller of the present invention reduces power consumption by suppressing clock signals to a display memory (comprising SGRAM or SDRAM) between screen refreshes and memory accesses. The present invention takes advantage of power-down modes provided for SGRAM and/or SDRAM memories which are used in the prior art to place a memory in an active suspend mode. Further energy savings are realized and memory bandwidth increased when using a display memory comprising two banks. When one bank of memory is being accessed, the other bank of memory is precharged and activated. Succeeding pages of memory are placed in alternate banks of display memory. Thus, then data is to be accessed from a next page of memory, the corresponding bank is already charged and ready to be accessed.

Method and apparatus for optimizing power consumption and memory

A method and apparatus for compensating crosstalk in liquid crystal displays is disclosed which involves applying boost voltages to the rows and columns of the display in proportion to the number of ON pixels in a row or column, the number of transition between 'ON-and-OFF' or 'OFF-and-ON' in each column, and the position of the pixel in a row. 'Boost' voltages are applied to each row as it is being actively scanned to provide horizontal crosstalk compensation, while 'boost' voltages are applied to each column during the vertical retrace interval of the display sequence to provide vertical crosstalk compensation. In a preferred embodiment, the vertical crosstalk compensation is determined during the vertical retrace interval over several flames.

Method and apparatus for compensating crosstalk in liquid crystal

A computer video controller, particularly a VGA or SVGA video controller for use with graphical user interface (GUI) software such as WINDOWS.TM. or OS/2.TM. is provided with two video data pipelines for simultaneously displaying full motion video within a window in a video display. A first data pipeline displays background video at a first pixel depth. A second data pipeline is provided to display a motion video window at a second, usually higher, pixel depth. The location of the motion video window is measured horizontally in number of memory fetch cycles needed to retrieve the horizontal scan line of pixel data abutting the motion video window. The width of the motion video window is measured in the number of memory fetches required to retrieve one scan line of the motion video window. By providing two parallel data pipelines having equal delays, the motion video window can be generated by selectively retrieving background pixel data or motion video window pixel data and transferring the data to the appropriate pipeline. In an alternative embodiment, data tags may be used to distinguished between background and motion video window pixel data. The controller may also support various compression formats for motion video.

Variable pixel depth and format for video windows

A video controller receives character data, attribute data and font data, each of which are stored in different planes of a video memory. The font data comprises bit maps of at least two character fonts, which may be user fonts or default fonts loaded from a controller BIOS. The video controller retrieves the font data, translates the font data into a page mode, and stores the font data in a hidden font cache in an unused portion of the video memory. The paged font data is divided into a number of pages equal to the number of scan lines per character. Each page contains a number of words, and each word contains at least two bytes. Each byte represents one scan line of a character in a different font. The video controller retrieves the paged fonts in page mode and assembles the scan lines for the characters to be displayed into one video scan line. The use of the page mode increases refresh rate and allows simultaneous display of two fonts.

Growing community of inventors

San Jose, CA, United States of America

Rakesh Kumar Bindlish