Texas Instruments Corporation

Rakesh Hariharan

Anant Shankar Kamath

Mark Edward Wentroble

Suzanne Mary Vining

Sumantha Manoor Madhyastha

Christopher Joseph Rodrigues

Swaminathan Sankaran

Robert Floyd Payne

Siraj Akhtar

Kumar Anurag Shrivastava

Mayank Garg

Tarunvir Singh

Suvadip Banerjee

Lakshmanan Balasubramanian

Bharath Kumar Singareddy

Kishalay Datta

Guha Lakshmanan

Soumi Paul

Kanteti Amar

Rr Manikandan

Vivekkumar Ramanlal Vadodariya

Gurumurti Kailaschandra Avhad

Prajwala Puttappa

Prajwala P

In an example, a method of operating a repeater having an isolation barrier to isolate a host side of the repeater from a peripheral side of the repeater, the repeater operable to be coupled to a universal serial bus (USB), includes causing the host side to enter into a suspend mode. The method also includes, responsive to entering the suspend mode, disabling a host isolation transceiver at the host side. The method includes periodically enabling the host isolation transceiver to transmit a data signal from the host side to the peripheral side. The method includes exiting the suspend mode. The method also includes enabling the host isolation transceiver.

USB suspend mode in isolated USB repeater

A packaged electronic device has a die with a load circuit, a resistor and an analog to digital converter (ADC). The resistor is coupled between a supply node of the die and a power input of the load circuit. The ADC has a first input coupled to a first terminal of the resistor, and a second input coupled to a second terminal of the resistor to measure a voltage across the resistor while a supply voltage is applied to the supply node to determine a load current conducted by the load circuit. A method of manufacturing a packaged electronic device includes wafer processing to fabricate the load circuit, the resistor and the ADC on or in a die area of the wafer with the resistor coupled between the power input of the load circuit and the supply node of the die area.

On-chip current sensor

An example apparatus includes: a pullup circuit coupled to a first USB terminal; a first pulldown circuit coupled to the first USB terminal; a second pulldown circuit coupled to a second USB terminal; a third pulldown circuit coupled to a third USB terminal; a fourth pulldown circuit coupled to a fourth USB terminal; a high-speed termination detection circuit including: a current source including a first supply terminal and a second supply terminal, the first supply terminal coupled to the first USB terminal, the second supply terminal coupled to the second USB terminal; a first comparator including a first comparator terminal and a second comparator terminal, the first comparator terminal coupled to the first USB terminal; and a second comparator including a third comparator terminal and a fourth comparator terminal, the third comparator terminal coupled to the second USB terminal; and a controller including a first control terminal and a second control terminal, the first control terminal coupled to the second comparator terminal, the second control terminal coupled to the fourth comparator terminal.

Methods and apparatus to detect L2 entry and reset in universal serial bus repeaters

A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

Dual role support for a high-speed capable USB repeater

An system-on-a-chip ('SoC') is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.

Stackable timer

Various configurations of high-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral, and methods of operating the same, are provided to improve the Remote Wake sequence. Repeaters include circuitry to detect the start of Resume signaling or the end of Resume, following initiation of Remote Wake. In an example, pull-up resistors coupled to upstream differential signal lines and a detection circuit with a current source are controlled to detect the start of Resume signaling. In another example, the upstream-side pull-resistors and an enable signal to an upstream-side transmitter are controlled to detect the end of Resume.

Universal serial bus repeater with improved remote wake capability

An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels. The front end circuitry on the other side of the isolation barrier decodes the two-state signals received over the one or more FS isolation channels and the two-state signals received over the HS isolation channel for transmission at its external terminals.

Isolated universal serial bus repeater with high speed capability

In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

Self-calibrating on-off keying based digital isolator

A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

Detection of a power state change in a serial bus repeater

Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

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Bengaluru, India

Rakesh Hariharan