Altera Corporation

Other

Quickturn Design Systems, Inc.

Prom Ks Mgmt Limited Liability Company

Prominence Networks, Inc.

Prom Ks Limited Liability Company

Quickturn Design

Rakesh H Patel

Sergey Yuryevich Shumarayev

Wilson Wong

Chong H Lee

John E Turner

Kevin A Norman

Ramanand Venkata

Tony K Ngai

Wei-Jen Huang

Stephen Paul Sample

Michael R Butts

James G Schleicher

Victor Maruri

Bruce B Pedersen

Tim Tri Hoang

William W Bereza

Vinson Chan

John D Lam

Henry Y Lui

Thomas Henry White

Jim Park

Simardeep Maangat

Chao Chiang Chen

David Wolk Mendel

Michael David Hutton

Tin H Lai

Andrew Leaver

Peter J Kazarian

Raminda U Madurawe

Thungoc M Tran

James D Sansbury

Tad Kwasniewski

Peter J Wright

Christopher J Pass

Kazi Asaduzzaman

Siddhartha Nag

Naveed Alam

James Park

Alfred D'Souza

Malik Kabani

Myron Wai Wong

Shankar Sinha

Arch Zaliznyak

Bill W Bereza

Sammy S Cheung

Edward Aung

Erhard Joachim Pistorius

Francis Man-Chit Chow

Paul Butler

Shoujun Wang

John C Costello

Mei Luo

Giles V Powell

Albert Vareljian

Binh Ton

Jingcheng Zhuang

Qingjin Du

Michael Hsiao-Ming Chu

Stjepan William Andrasic

Richard G Cliff

Srinivas T Reddy

Ning Xue

Bruce B Pederson

Yuming Tao

Miao Li

Apparatus and methods are described for space-efficient, high-speed data communications for integrated circuits. Bandwidth is multiplied by using multiple individual wireline communications channels coupled to form a communications lane. The data receiver for a channel implements symbol-rate equalization and crosstalk filtering that is space efficient, allowing high-speed data communications to be added as an ancillary function to an IC.

Self-tuning high speed transceiver for IC wireline channel

In one aspect, a memory circuit is provided. The memory circuit includes a first memory device; a second memory device coupled to the first memory device; a freeze circuit coupled to a first output terminal and a second output terminal, where the first output terminal is an output terminal of the first memory device and the second output terminal is an output terminal of the second memory device; and a test switch coupled to the first output terminal and the second output terminal.

Memory circuit including memory devices, a freeze circuit and a test switch

A graphical user interface (GUI) is disclosed that allows a user to identify routers, communities, residents and media aggregation managers existing on a network. The user may interactively select a path that includes two media aggregation managers and at least one router. The GUI predicts scheduled bandwidth utilization along the selected path for a variety of residents wishing to communicate across the path. The GUI may be utilized for initializing all media aggregation managers on the network along with provisioning each of the routers on the selected path. The GUI provisions all of the routers and initializes all of the media aggregation managers on the selected path simultaneously in order to accomplish the predicted schedule of usage provided by the GUI to the user and force all communication packets communicated between the residents to travel along the selected path.

Graphical user interface (GUI) for administering a network implementing media aggregation

A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.

Stacked die network-on-chip for FPGA

An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral region of the top surface. A number of through-silicon-vias are distributed within the peripheral region and a set of TSVs are formed within the non-peripheral region of the integrated circuit. Conducting lines on the bottom surface are coupled between each peripheral through-silicon-via and a corresponding non-peripheral through-silicon-via. Power is distributed from the conducting pads to the TSVs within the non-peripheral region through the TSVs within the peripheral region, thus supplying power and ground to circuits located within the non-peripheral region of the integrated circuit chip.

Distributing power with through-silicon-vias

High-speed serial data transceiver circuitry on a programmable logic device ('PLD') includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop ('PLL') circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer ('FFE') circuitry and decision-feedback equalizer ('DFE') circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.

High-speed data reception circuitry and methods

Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.

Digital equalizer for high-speed serial communications

In one aspect, a memory circuit is provided. The memory circuit includes a first three-terminal (3T) resistive memory device and a second 3T resistive memory device coupled to the first 3T resistive memory device. In another aspect a memory array with memory circuits having 3T devices is provided. In yet another aspect, a method of programming a memory array is provided.

3T device based memory circuits and arrays

A semiconductor system in a package in which at least first and second semiconductor substrates are mounted one above the other on a package substrate. The first substrate is mounted on the package substrate with its active (or front) side facing the package substrate. A plurality of through-silicon-vias (TSVs) extend through one or more peripheral regions of the first substrate; and a redistribution layer is located on the back side of the first substrate and connected to the TSVs. The second substrate is mounted on the first substrate and electrically connected to circuits in the active side of the first substrate through the redistribution layer and the TSVs. Illustratively, one of the substrates is an FPGA and one or more of the other substrates stores the configuration memory and/or other functional memory for the FPGA.

Stacked semiconductor substrates

The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

Method and apparatus for multi-mode clock data recovery

Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.

Decision feedback equalization for variable input amplitude

A semiconductor system in a package in which at least first and second semiconductor substrates are mounted one above the other on a package substrate. The first substrate is mounted on the package substrate with its active (or front) side facing the package substrate. A plurality of through-silicon-vias (TSVs) extend through one or more peripheral regions of the first substrate; and a redistribution layer is located on the back side of the first substrate and connected to the TSVs. The second substrate is mounted on the first substrate and electrically connected to circuits in the active side of the first substrate through the redistribution layer and the TSVs. Illustratively, one of the substrates is an FPGA and one or more of the other substrates stores the configuration memory and/or other functional memory for the FPGA. Advantageously, design costs are reduced by using pre-existing designs and modifying them as needed to provide TSVs along the periphery of the circuit.

Growing community of inventors

Cupertino, CA, United States of America

Rakesh H Patel