Freescale Semiconductor,inc.

Rakesh Bakhshi

Robert N Ehrlich

Darrell L Carder

Bipin Duggal

Dhiraj Maheshwari

Gulshan Kumar Miglani

A method of ganging memories in an Integrated Circuit (IC) design identifies a first subset of a first set of the memories that have word counts in a common power of two range, a common count of memory blocks, and a common column multiplexing factor, a first memory that does not have a word count in the common power of two range, a second memory of the first set of memories that does not have at least one of a common count of memory blocks and a common column multiplexing factor, and then inserts a common scrambling unit, a common chip select unit, a common comparator, a common repairing unit, a first scrambling unit, a second scrambling unit, a first comparator, and a first repairing unit into the IC design.

Method of grouping embedded memories for testing

The present disclosure provides system and method embodiments for generation of capture clock signals. A first and second test circuit receive a first test pattern and a functional clock signal. A first test clock control (TCC) circuit of the first test circuit generates a first capture clock signal that comprises a set of functional clock signal pulses generated according to a first clock pattern of the first test pattern. A second TCC circuit of the second test circuit generates a second capture clock signal that comprises the set of functional clock signal pulses generated according to the first clock pattern. The set of functional clock signal pulses of the second capture clock signal are staggered in time from the set of functional clock signal pulses of the first capture clock signal.

Scan testing with staggered clocks

A system and method for testing a plurality of memory blocks in a System on Chip (SOC) design uses two Test Access Ports (TAPs); a user TAP and an EDA tool TAP, to provide instructions and test data to the SOC. The system includes a glue logic block, a secured logic block and a memory testing module. The glue logic block selects the user TAP at the outset of the testing phase. The secured logic block is coupled with the user TAP and generates a TAP selection signal, which controls the selection of the EDA tool TAP. The memory testing module is used to carry out the process of testing the memory blocks when the EDA tool TAP is selected.

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Faridabad, India

Rakesh Bakhshi