Intel Corporation

Zoran Corporation

Rakefet Kol

Shai Rotem

Ran Ginosar

Peter A Beerel

Kenneth Scott Stevens

Christopher John Myers

Kenneth Yi Yun

Edwin Jan Van Dalen

Amit Gur

Tamir Klein

Rony Zatzarinni

Jacob Finkelstein

Pavel Kounitsky

Hadas Dahan

Itai Ostashinsky

Asa Levinger

Guy Berger

A device, method, system, or article has multi-directional rolling cache to store image data.

Multi-directional rolling cache and methods therefor

An apparatus for a near lossless compression scheme is described herein. The apparatus includes an image processing pipeline and a compressor. The image processing pipeline is to apply a plurality of processing stages to high dynamic range images to output a plurality of intermediate processed images, wherein each image comprises a plurality of pixel components. The compressor is to generate compression tiles of the plurality of intermediate processed images, wherein each output of the plurality of processing stages is compressed independently of the other processing stage.

Near lossless compression scheme and system for processing high dynamic range (HDR) images

Techniques related to multi-block memory reads for image de-warping are discussed. Such techniques may include copying pixel data corresponding to overlapping regions of memory between adjacent image modification regions from a local buffer and retrieving pixel data corresponding to non-overlapping regions from external memory.

Multi-block memory reads for image de-warping

In a device that utilizes a memory device, the access bandwidth of the memory device is efficiently utilized by determining a set of operations to be performed on information stored in the memory device, and sorting the operations into an order so as to minimize the number of accesses to the memory device to perform the operations. The sorted operations are then performed in that order. An example of such a device is an error correction decoder, such as for use with an optical disk reader or player. The error correction decoder generates error correction data, representing error correction operations, and sorts the error correction data into multiple sets, each set for correcting the errors in a respective row of an ECC block stored in an external buffer. The error correction operations are then performed row by row.

System and method for efficient use of memory device bandwidth

Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.

Apparatus and method for parallel processing and self-timed serial

A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

Apparatus and method for self-timed marking of variable length

A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.

Efficient self-timed marking of lengthy variable length instructions

An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.

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Rakefet Kol