Samsung Electronics Co., Ltd.

Raju Udava

Tushar Vrind

Balaji Somu Kandaswamy

Venkata Raju Indukuri

Vinay Kumar Shrivastava

Diwakar Sharma

Rohit Kumar

Lalit Kumar Pathak

Samir Kumar Mishra

Nikhil Patni

Debasish Das

Lakshmi Prasanna Jasti

Manan Dixit

Patana Bhagwan Reddy

Venakata Raju Indukuri

A method for load balancing in a multi-core processor of an electronic device, the method including dividing, by the electronic device, a first task and at least one second task into a plurality of task-jobs, determining, by the electronic device, at least one core configuration for each of the plurality of task-jobs, scheduling, by the electronic device, each of the plurality of task-jobs on at least one core of the multi-core processor based on the at least one core configuration to generate an execution schedule, and executing, by the multi-core processor, the plurality of task-jobs according to the execution schedule.

Electronic devices and methods for 5G and B5G multi-core load balancing

The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.

Method for reducing interrupt latency in embedded systems

A method and system for providing memory management in a Real-Time Operating System (RTOS) based system are provided. The method includes creating a plurality of tasks with a two level stack scheme comprising a first level stack and a second level stack, scheduling a first task for execution by moving a stack pointer from the first level stack to the second level stack, determining whether the first task is pre-empted, allocating the second level stack to the first task in a second state if the first task is not pre-empted, changing an active task for execution, determining whether the first task relinquishes control from the second state and is waiting for a resource, moving the stack pointer back from the second level stack to the first level stack if the first task relinquishes itself and providing the second level stack for use by a second task.

Method and system for providing stack memory management in real-time operating systems

A method of Physical Multicast Channel (PMCH) decoding for Multicast Broadcast Single Frequency Network (MBSFN) by a UE includes decoding a Transport Block (TB) in a first sub-frame of a Multicast Channel Scheduling Period (MSP) by a Physical (PHY) layer in the UE; providing the decoded TB to a Media Access Control (MAC) layer; performing blind decoding on all received MBSFN sub-frames, until the PHY layer receives PMCH scheduling configuration from the MAC layer; selecting at least one Logical Channel IDentifier (LCID) and Multicast Transport Channel (MTCH) scheduling information for each LCID by decoding a Multicast Channel Scheduling Information Protocol Data Unit (MSI PDU), the MSI PDU present in the decoded TB; building a PMCH scheduling configuration by the MAC layer based on the selected at least one LCID and the MTCH scheduling information; passing the PMCH scheduling configuration to the PHY layer by the MAC layer; and applying the PMCH scheduling configuration.

Method and system for decoding MBSFN data

Method and apparatuses are provided for providing preemptive task scheduling for a Real Time Operating System (RTOS). A two-level priority is assigned to each task that is created. The two-level priority includes a kernel priority and a user-defined priority. A priority bitmap corresponding to the kernel priority is created. A priority bit in the priority bitmap is enabled. The priority bit indicates a status of a respective task.

Method and apparatus for providing a preemptive task scheduling scheme in a real time operating system

Growing community of inventors

Bengaluru, India

Raju Udava