Intel Corporation

Rajshree Chabukswar

Michael W Chynoweth

Russell Jerome Fenger

Ahmad Yasin

Deepak Samuel Kirubakaran

Monica Gupta

Eliezer Weissmann

Beeman C Strong

Jianfang Olena Zhu

Zhongsheng Wang

Eugene Gorbatov

James G Hermerding, Ii

Chee Lim Nge

Sudheer Nair

William A Braun

Raoul Rivas Toledano

Muhammad Taher

Udayan Kapaley

Richard B O'Connor

Michael Mishaeli

Tsvika Kurts

Ofer Levy

Julius Yuli Mandelblat

Itamar S Kazachinsky

Jianwei Dai

Anthony Wojciechowski

Avner Lottem

Vikas R Vasisht

Guruprasad Settuvalli

Efraim Rotem

Jason W Brandt

Andrew J Herdrich

Atsuo Kuwahara

Jeremy J Shrall

Guy M Therien

Jonathan D Combs

Premanand Sakarda

Andreas Kleen

Toby Opferman

Hisham Abu Salah

Ahmad A Samih

Muhammad Abozaed

Ashraf H Wadaa

Vijay Dhanraj

Richard R Winterton

Vijay Bahirji

Shadi T Khasawneh

Mukund Ramakrishna

Nir Misgav

Ivan Chen

John M Esper

Balaji Masanamuthu Chinnathurai

Refael Mizrahi

Renji Thomas

Sze Ling Yeap

Charlie J Hewett

Ramakrishnan Sivakumar

Christopher Mark Chrulski

Chris Binns

Ahmed Shams

Nicholas Klein

Jumnit Hong

Sneha Gohad

Chad Gutierrez

Houfei Chen

Joseph K Olivas

Omer Barak

Sumant Tapas

Meghana Gudaram

Raj Kumar Subramaniam

Christine M Lin

Embodiments of apparatuses, methods, and systems for resource control based on software priority are described. In embodiments, an apparatus includes resource sharing hardware and multiple cores. The resource sharing hardware is to share the shared resource among the cores. A first core includes first execution circuitry to execute multiple threads. The first core also includes registers programmable by software. A first register is to store a first identifier of a first thread and a first priority tag to indicate a first priority of the first thread relative to a second priority of a second thread. A second register to store a second identifier of the second thread and a second priority tag to indicate the second priority of the second thread relative to the first priority of the first thread. The resource sharing hardware is to use the first priority and the second priority to control access to the shared resource by the first thread and the second thread.

Autonomous and extensible resource control based on software priority hint

Methods and apparatus for bi-directional control of computing unit frequency are disclosed. An example apparatus to control a frequency of a computing unit includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to determine a performance hint from a first register, the performance hint corresponding to a requested performance of the computing unit for executing a thread associated with software, determine power and performance (PnP) statistics pertaining to the thread from a second register, control the frequency of the computing unit based on the performance hint and the PnP statistics, and provide a pressure of the computing unit to the software.

Methods and apparatus for bi-directional control of computing unit frequency

An embodiment of an integrated circuit may comprise an instruction decoder to decode one or more instructions to be executed by a core, and circuitry coupled to the instruction decoder, the circuitry to determine if a decoded instruction involves a page to be fetched, and determine one or more hints for one or more optional pages that may be fetched along with the page for the decoded instruction. Other embodiments are disclosed and claimed.

Core-based speculative page fault list

A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

Precise longitudinal monitoring of memory operations

A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

Hardware and software coordinated cost-aware low power state selection

In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

System, apparatus and method for dynamically adjusting platform power and performance based on task characteristics

Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.

Performance monitoring in heterogeneous systems

Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

Methods and apparatus to manage energy usage and compute performance

The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Operating system assisted prioritized thread execution

A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

Technology for optimizing hybrid processor utilization

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

Apparatus and method for adaptively scheduling work on heterogeneous processing resources

A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.

Modifying processor frequency based on interrupt rate

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Sunnyvale, CA, United States of America

Rajshree Chabukswar