Raytheon Company

Rajni Kant

Deepak Mehrotra

Gerard J Shaw

Jok Y Go

Kun-Nau Chen

Kishor M Patel

An integrated circuit having an array of logic gates adapted to provide predetermined logic functions on a plurality of input logic signals fed to the gate array and produce such predetermined logic functions as output signals at a plurality of array output terminals. A plurality of output buffer circuits are coupled between the outputs of an interconnected gate and the array output terminals. A circuit is provided for electrically decoupling each one of the plurality of logic output buffer circuits from the plurality of array output terminals in response to a common control signal. In a preferred embodiment, the control signal is fed to a single one of the plurality of array output terminals. With such arrangement, in response to the control signal, all logic outputs of the gate array are electrically isolated from other components wired to the gate array thereby allowing diagnostic testing of these other components in spite of the fact that they are wired to the gate array. It also allows parametric testing of three-state condition of the buffers required to be three-state buffers by the customer for normal device operation.

Configurable logic gate array

A configurable logic gate array having an array of logic gates adapted for selective electrical interconnection to provide a predetermined logic function on a plurality of input logic signals fed to the configured gate array and produce such predetermined logic function as an output signal at an array output terminal. An output buffer circuit is coupled between the output of an interconnected gate and the array output terminal. A parametric testing circuit is responsive to a control signal for electrically coupling, during a normal operating mode, the output of the interconnected gate to the array output terminal, or, during a parameter testing mode, a logic signal source for producing 'high' and 'low' logic output voltages representative of the logic output voltage produced by the logic gates in response to the logic input signals. With such arrangement, there is a reduction in the test program development time since bringing the output to the desired state (high or low) be sequencing through function testing to achieve the desired state on the desired pin (an error prone, time consuming process requiring full understanding of the logic implemented and rationale applied by customer in generating test vectors) is eliminated. Further, with such an arrangement, parametric testing of the output signals by the gates in the array is performed by merely driving each output buffer circuit to 'high' or 'low' logic states thereby reducing parametric testing time of the gate array after the logic gates have been selectively electrically interconnected to provide the desired predetermined logic function.

A semiconductor device fabrication process is provided wherein a first window is formed in a first silicon dioxide layer which is disposed over the surface of a silicon layer to expose a first portion of the silicon layer. A doped region is formed in the first portion of a silicon layer exposed by the first window. A second layer of silicon dioxide is deposited over the surface of the first, previously formed, silicon dioxide layer and over the first portion of the silicon layer exposed by the first window. A second window is formed through the first and second silicon dioxide layers to expose a second, different portion of the surface of the silicon layer. A layer of silicon nitride is disposed over the second layer of silicon dioxide and through the second formed window onto the portion of the silicon layer exposed by such second formed window. The surface of the structure is then masked with windows being formed in such mask over the first and second previously exposed portions of the silicon layer. An etchant is brought into contact with portions of the silicon nitride layer exposed by the windows formed in the mask to selectively remove the portions of the silicon nitride layer exposed by such windows and to thereby expose the portion of the second silicon dioxide layer disposed over the first exposed portion of the silicon layer and the second exposed portion of the silicon layer. A Schottky contact metal is deposited over the surface of the structure and onto the second exposed portion of the silicon layer to form a Schottky contact region. The portion of the second silicon dioxide layer disposed over the first exposed portion of the silicon layer is then selectively removed with a chemical etchant to expose a portion of the previously formed doped region.

Growing community of inventors

Milpitas, CA, United States of America

Rajni Kant