Texas Instruments Corporation

Rajkumar Sankaralingam

Muhammad Yusuf Ali

Ann Margaret Concannon

James Paul Di Sarro

Aravind Chennimalai Appaswamy

Gianluca Boselli

Charles M Branch

Krishna Praveen Mysore Rajagopal

Xianzhi Dai

James Paul DiSarro

Karmel Kranthi Nagothu

A lateral semiconductor controlled rectifier (SCR) includes a pwell and an nwell A plurality of p+ contact regions connect to the pwell and are spaced apart from one another by a dielectric material along a width of the pwell. There are a plurality of n+ contact regions connect to the nwell and are spaced apart from one another by dielectric material along a width of the nwell.

SCR having selective well contacts

A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.

Transient triggered active FET with surge immunity

An ESD protection system including structure to operate an IC during nominal conditions, to protect the IC during an ESD event, and to allow the IC to operate during slow rising input node voltages that exceed nominal conditions.

Electrostatic discharge protection system

An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp transistor coupled between the drain of the input/output transistor and the gate of the input/output transistor. An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp diode coupled between the drain of the input/output transistor and the gate of the input/output transistor and a biasing resistor coupled between the gate and source of the input/output transistor.

Compact ESD bootstrap clamp

An electrostatic discharge (ESD) protection integrated circuit (IC) includes a substrate having a semiconductor surface, a high power supply rail (VDD) and a low power supply rail (VSS) on the semiconductor surface. A trigger circuit including at least one trigger input and at least one trigger output is coupled between VDD and VSS. An active shunt including at least a large MOSFET is coupled between VDD and VSS. The trigger output is coupled to a gate electrode of the large MOSFET, and at least one diode or diode connected transistor (blocking diode) is coupled between VDD and the trigger circuit, within the trigger circuit or between the trigger output and gate electrode.

Active ESD protection circuit with blocking diode

An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.

ESD robust level shifter

A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion.

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Plano, TX, United States of America

Rajkumar Sankaralingam