Intel Corporation

International Business Machines Corporation

Rajkishore Barik

Balaji Vembu

Eriko Nurvitadhi

Nicolas C Galoppo Von Borries

Tsung-Han Lin

Kamal Sinha

Altug Koker

Xiaoming Chen

Abhishek R Appu

Joydeep Ray

Feng Chen

Sara S Baghsorkhi

Tatiana Shpeisman

Anbang Yao

Justin E Gottschlich

Narayan Srinivasa

Dukhwan Kim

Nadathur Rajagopalan Satish

Farshad Akhbari

Prasoonkumar Surti

Ben J Ashbaugh

Ping Tak Tang

Vasanth Ranganathan

Sanjeev S Jahagirdar

Elmoustapha Ould-Ahmed-Vall

Linda L Hurd

Kevin Nealis

Michael S Strickland

Brian T Lewis

Subramaniam M Maiyuran

Travis T Schluessler

Karthik Vaidyanathan

Adam T Lake

John H Feit

Jeffery S Boles

Devan Burke

Wenyin Fu

Josh B Mastronarde

Sanu K Mathew

Mark A Anders

Himanshu Kaul

John Charles Weast

Mike B Macpherson

Murali Sundaresan

Chandrasekaran Sakthivel

Jeremy Bottleson

Jeffrey R Jackson

Ali-Reza Adl-Tabatabai

Mike MacPherson

Tomasz Janczak

Jayanth N Rao

Dhawal Srivastava

Yang Ni

Richard Lewis Hudson

Stephan A Herhut

Rashid Kaleem

Leonard Truong

Jaswanth Sreeram

Narayan Biswal

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Pradeep Varma

Parul Alok Mittal

Krishna Nandivada Venkata

Manish P Kurhekar

Chunling Hu

One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

Compute optimizations for neural networks

A mechanism is described for facilitating efficient training of neural networks at computing devices. A method of embodiments, as described herein, includes detecting one or more inputs for training of a neural network, and introducing randomness in floating point (FP) numbers to prevent overtraining of the neural network, where introducing randomness includes replacing less-significant low-order bits of operand and result values with new low-order bits during the training of the neural network.

Training with adaptive runtime and precision profiling

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Instructions and logic to perform floating point and integer operations for machine learning

A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

Efficient thread group scheduling

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

Methods, apparatus, systems, and articles of manufacture are disclosed to steal work in heterogeneous computing systems. An apparatus includes load balancing circuitry to obtain tasks from a workload by encoding minimum and maximum index ranges of a data parallel operation, allocate a first task from the workload to a first work queue based on a first capability of first computation circuitry, the first computation circuitry to process the first task in the first work queue, and allocate a second task from the workload to a second work queue, second computation circuitry to process the second task in the second work queue. The apparatus further includes first work stealer logic to steal the second task from the second work queue using an atomic operation to access the second work queue.

Work stealing in heterogeneous computing systems

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.

Machine learning sparse computation mechanism

One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

One embodiment provides for a general-purpose graphics processing unit including a scheduler to schedule multiple matrix operations for execution by a general-purpose graphics processing unit. The multiple matrix operations are determined based on a single machine learning compute instruction. The single machine learning compute instruction is a convolution instruction and the multiple matrix operations are associated with a convolution operation.

Specialized fixed function hardware for efficient convolution

A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine an optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

Tool for facilitating efficiency in machine learning

Growing community of inventors

Santa Clara, CA, United States of America

Rajkishore Barik