International Business Machines Corporation

Globalfoundries Inc.

Rajiv V Joshi

Louis L Hsu

Sudipto Chakraborty

Rouwaida N Kanj

Louis C Hsu

Sani Richard Nassif

Keunwoo Kim

Bruce Bennett Doris

Yuen H Chan

Emrah Acar

Tong Li

Chih-Chao Yang

Jack Allan Mandelman

Carl John Radens

Jente Benedict Kuang

Steven J Holmes

Jerome J Cuomo

Hormazdyar M Dalal

Anirudh Devgan

Wei Hwang

Naigang Wang

Swaminathan Balasubramanian

Hung Cai Ngo

Richard Quimby Williams

William Robert Reohr

Donald W Plass

Werner A Rausch

Fariborz Assaderaghi

Azeez Jennudin Bhavnagarwala

Dan Moy

Ping-Chuan Wang

Toshiaki Kirihata

Wayne Frederick Ellis

Stephen Victor Kosonocky

Russell J Houghton

Jae-Joon Kim

Ching-Te Kent Chuang

Zhijian Yang

Antonio R Pelella

Gregory J Fredeman

Oleg Gluschenkov

John Atkinson Fifield

Philip George Emma

Robert C Wong

Ruchir Puri

Fook-Luen Heng

Edward J Nowak

Terence B Hook

Alper Buyuktosunoglu

Pradip Bose

Hubertus Franke

Subramanian Srikanteswara Iyer

Wilfried Haensch

Alan Edward Rosenbluth

Pranita Kerber

Kafai Lai

Anthony Correale, Jr

Edward William Kiewra

Chun-Yung Sung

Rama Divakaruni

James Gardner Ryan

Joseph F Shepard

Rama Nand Singh

Kaushik Roy

Terry I Chappell

Kehan Tian

Saeed Reza Bagheri

Swagath Venkataramani

Ruilong Xie

Daniel C Edelstein

William R Tonti

Dureseti Chidambarrao

Sang Hoo Dhong

Baozhen Li

Kerry Bernstein

Dominic Joseph Schepis

Leland Chang

Daniel Joseph Friedman

Zhuo Li

Ying Liu

Louis Lu-Chen Hsu

Ravikumar Ramachandran

Robert H Dennard

Kevin John Nowka

John Francis Bulzacchelli

Vishnubhai Vitthalbhai Patel

Juergen Pille

Osamu Takahashi

Paul Christian Parries

Yasunao Katayama

Matthew R Wordeman

James A Culp

Alan J Drake

Chad Allen Adams

Bernard S Meyerson

Rolf Sautter

David James Frank

David R Hanson

Robert Rosenberg

Sukhvinder Singh Kang

A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.

Semiconductor backside transistor integration with backside power delivery network

An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.

Short circuit detection in a read/write assist capacitor of a memory

An apparatus includes a memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, coupled to the plurality of word lines and the plurality of bit line pairs, and located at the plurality of cell locations. A plurality of word line drivers are coupled to the plurality of word lines, a dynamic voltage boost is coupled to the memory array, and a controller is coupled to the plurality of word line drivers and the dynamic voltage boost. The controller is configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation.

Reconfigurable data processing and storage unit for deep neural networks

A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Current mode signal path of an integrated radio frequency pulse generator

A wireless power system includes a phase locked loop (PLL) providing an input signal tuned in frequency, a plurality of dividers coupled to the PLL to divide the frequency of the input signal, a plurality of phase interpolators electrically connected to the plurality of dividers to generate multiple phases based on the input signal, and a plurality of drivers electrically connected to the plurality of phase interpolators to direct a plurality of output signals each having a different frequency to a plurality of sensor clusters, each sensor cluster operating at a different frequency.

Wireless power for sensor arrays

Mechanisms are provided for optimizing remuneration for computing services. Computing services are registered which stores registration data comprising remuneration associations between computing services and consumers. A hierarchical computer model is generated based on the registration data, where the model represents dependencies between consumers and providers of computing services. For a service request from a consumer, each transaction with each computing service in a service invocation chain associated with the service request is identified and a cost of each transaction is calculated. The calculated cost of the service invocation chain is optimized based on applying an optimization algorithm to a cost function applied to a selected portion of the hierarchical computer model corresponding to the service invocation chain.

Computer service invocation chain monitoring and remuneration optimization

Transmitters and methods of transmitting a polar-modulated signal include a driver to output a polar-modulated signal according to a phase-modulation signal and an amplitude-modulation signal. A voltage regulator is connected to the driver, with the amplitude-modulation signal controlling an input of the voltage regulator and with the amplitude-modulation signal further being combined with an output of the voltage regulator to control an amplitude of the output of the driver to compensate for bandwidth cutoff noise in the voltage regulator.

High-efficiency transmitter

A singled ended current sense amplifier circuit including an input stage having a bitline node, a sense node and a feedback circuit comprising a feedback inverter configured to provide an amplified voltage from the bitline node. The feedback inverter may include first and second NMOS transistors serially connected to a feedback node and first and second PMOS transistors serially connected to the feedback node. The feedback circuit may include a third NMOS transistor having a gate terminal connected to the feedback node and a drain terminal connected to the sense node. The input stage may include a third PMOS transistor operating as a current source to generate a sense current which flows in a current sensing path between the sense node and the bitline node. The input stage may act as a regulator to keep the voltage at the bitline node constant.

Single ended current mode sense amplifier with feedback inverter

An apparatus includes a plurality of signal processing stages configured to convert a digital baseband signal into an analog radio frequency signal for transmission. The signal processing stages are configured to be operatively coupled to a positive supply voltage and a negative supply voltage. At least one signal processing stage of the plurality of signal processing stages is configured to generate an analog voltage signal which comprises a voltage level that is outside of a voltage range defined by the positive supply voltage and the negative supply voltage.

Transmitters with dynamic ranges extending beyond supply rails

A quantum write controller includes an in-phase path that includes a first digital to analog converter (DAC) configured to receive an in-phase signal at a first frequency, a first mixer configured to create a third in phase frequency, a first combiner configured to combine an output of the first mixer with an output of a third mixer, and a second mixer configured to mix an output of the first combiner with a fourth in phase frequency. There is a quadrature path that includes a second DAC configured to receive a quadrature phase signal at the first frequency, a third mixer configured to create a third quadrature frequency, a second combiner configured to combine the output of the third mixer with the output of the first mixer, and a fourth mixer configured to mix an output of the second combiner with a fourth quadrature frequency.

Low power quantum controller

An improved electronic mixed mode multiplier and accumulate circuit for artificial intelligence and computing system applications that perform vector-vector, vector-matrix and other multiply-accumulate computations. The circuit is provided is a high resolution, high linearity, low area, low power multiply&#x2014;accumulate (MAC) unit to interface with a memory device for storing computation output results. The MAC unit uses a less number of current carrying elements resulting in much lower integrated circuit area, and provides a tight matching between the current elements thus preserving inherent linearity requirements due to current mode operation. Further the MAC performs current scaling using switches and current division where the current switches occupy minimum size transistors requiring a small area to implement that renders it compatible with MRAM such as a magnetic tunnel junction device. The MAC is hierarchically extended for increased number of bits to provide a delay implementation using orthogonal vector and current addition.

Low area multiply and accumulate unit

A sense amplifier circuit includes a bitline node, a sense node, and a feedback circuit which is connected to the bitline node and to the sense node. The feedback circuit includes a cascode-connected pair of transistors configured to isolate the bitline node from an occurrence of a voltage variation on the sense node.

Single ended bitline current sense amplifiers

An apparatus includes multiple signal paths for signal transmission, and control circuitry. The multiple signal paths include a first signal path and a second signal path. The first signal path is configured to convert a digital baseband signal to a first radio frequency (RF) signal having a first frequency and a first gain. The second signal path is configured to convert a digital baseband signal to a second RF signal having a second frequency and a second gain, wherein the second gain is less than the first gain. The control circuitry is coupled to the plurality of signal paths and is configured to receive one or more control signals to enable selective activation of at least one signal path of the plurality of signal paths.

Transmitter with multiple signal paths

Transmitters, sensor systems, and methods of transmission include a frequency adjuster coupled to a ring oscillator to reduce latency and power consumption and to receive a signal from the ring oscillator. The frequency adjuster includes logic circuits to adjust the signal to a selected transmission frequency band. A band switch is coupled to the ring oscillator and the frequency adjuster to select logic circuits within the frequency adjuster to determine the selected transmission frequency band from a set of output frequency bands. A first radio front end is coupled to the frequency adjuster to transmit the signal on the selected transmission frequency band.

Efficient multi-band transmitter

Systems and methods for monitoring current anomaly are described. In an example, a device can measure first current flowing along a first liner between an instrument to an equipment. The device can measure second current flowing along a second line between the equipment to the instrument. The device can compare the measurements of the first current and the second current. The device can identify a presence of current anomaly based on the comparison of the measurements of the first and second currents. The device can, in response to the presence of the current anomaly, disconnect the instrument from the equipment.

Protection adapter for oscilloscope probes

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Yorktown Heights, NY, United States of America

Rajiv V Joshi