Cypress Semiconductor Corporation

Parade Technologies, Ltd.

Rajiv Singh

Harold Kutz

Eashwar Thiagarajan

Erhan Hancioglu

Eric N Mann

Amsby D Richardson, Jr

Andrew C Page

Bert Sullam

Masashi Kijima

Vaibhav Ramamoorthy

Timothy John Williams

Andriy Maharyta

Jonathan R Peterson

Kendall V Castor-Perry

Kaveh Hosseini

David Goniodsky

Kendall Castor-perry

A noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) including a noise-shaping (NS) filter, a comparator, a differential input path between the NS filter and the comparator, and a cross-coupled set of capacitive elements coupled to the differential input path.

Noise shaping successive-approximation register (SAR) analog-to-digital converter (ADC)

Systems, methods, and devices enhance management of components used in data converters. Methods include receiving an input at a data converter comprising a digital to analog converter (DAC), the digital to analog converter comprising a plurality of sensing elements, and performing, using the DAC, a first conversion operation based on the input and a first set of the plurality of sensing elements identified by a first pointer value. Methods also include determining a pointer increment value based, at least in part, on an output of the first conversion operation and a hysteresis threshold value, the pointer increment value being used to determine an amount by which the first pointer value is incremented, the hysteresis threshold value identifying a threshold for determination of the pointer increment value.

Systems, methods, and devices for data converter management

Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.

Ultra-low power adaptively reconfigurable system

An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Programmable chopping architecture to reduce offset in an analog front end

Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.

A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.

Method for fast detection and automatic gain adjustment in ADC based signal

A method can include, amplifying an analog input signal to generate an amplified analog signal; modulating the amplified analog signal into a digital data stream; filtering the digital data stream with a first digital filter to generate a first filtered data stream, and selectively changing a gain of the amplifier in response to the first filtered data stream. While the digital data stream is filtered with the first digital filter, the digital data stream is filtered with a second digital filter to generate a second filtered data stream. An output digital value corresponding to the analog input signal in response to the second filtered data stream. Corresponding systems and devices are also disclosed.

A method for compensating for panel capacitance the associated current is proposed, wherein the mutual capacitances of a capacitance sensing array are selectively coupled to drive voltages and to a self capacitance under test.

Growing community of inventors

Lynnwood, WA, United States of America

Rajiv Singh