Advanced Micro Devices Corporation

Globalfoundries Inc.

Rajiv M Hattangadi

David B Witt

H S Ramagopal

Alan F Hendrickson

Carlin D Cabler

Muralidharan Santharaman Chinnakonda

Herbert M Chen

Hebbalalu S Ramagopal

Larry Alan Woodrum

Mysore Raguveer

Ashwin I Matta

An apparatus for performing speculative stores is provided. The apparatus reads the original data from a cache line being updated by a speculative store, storing the original data in a restore buffer. The speculative store data is then stored into the affected cache line. Should the speculative store later be canceled, the original data may be read from the restore buffer and stored into the affected cache line. The cache line is thereby returned to a pre-store state. In one embodiment, the cache is configured into banks. The data read and restored comprises the data from one of the banks which comprise the affected cache line. Instead of forwarding store data to subsequent load memory accesses, the store is speculatively performed to the data cache and the loads may subsequently access the data cache. Dependency checking between loads and stores prior to the speculative performance of the store may stall the load memory access until the corresponding store memory access has been performed. Similar functionality to forwarding of store data is obtained through the performance of load memory accesses to the data cache. Additionally, speculative load memory accesses which are partially overlapped by a prior speculative store memory access may be performed more efficiently.

Apparatus and method for performing speculative stores

A superscalar microprocessor employing a data cache configured to perform store accesses in a single clock cycle is provided. The superscalar microprocessor speculatively stores data within a predicted way of the data cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete, utilizing a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output. Therefore, the access time of the associative data cache may be substantially similar to a direct-mapped cache access time. The superscalar microprocessor may therefore be capable of high frequency operation.

Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle

Apparatus and method performing speculative stores

Superscalar microprocessor employing a data cache capable of performing

A method is herein provided for placing drivers and repeaters along the interconnect so as to optimize interconnection propagation delay with respect to area and time constraints. The method provided optimizes the propagation delay and simplifies the propagation delay determination by first using drivers to divide an interconnect into forkless branches, then linearizing the delay of each branch by placing repeaters along the length of the branches.

Method for optimization of multi-level interconnect RC delay

A data cache configured to perform store accesses in a single clock cycle is provided. The data cache speculatively stores data within a predicted way of the cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete. If the way prediction is incorrect, then the captured data is restored to the predicted way. If the store access hits in an unpredicted way, the store data is transferred into the correct storage location within the data cache concurrently with the restoration of data in the predicted storage location. Each store for which the way prediction is correct utilizes a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output. Therefore, the access time of the associative data cache may be substantially similar to a direct-mapped cache access time. The present data cache is therefore suitable for high frequency superscalar microprocessors.

Data cache which speculatively updates a predicted data cache storage

Apparatus for speculatively storing and restoring data to a cache memory

A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Memory operations are selected from the load/store buffer for access to the data cache, including cases where the memory operation selected is subsequent in program order to a memory operation which is known to miss the data cache and is stored in the buffer. In this way, other memory operations that may be waiting for an opportunity to access the data cache may make such accesses, while the memory operations that have missed await an opportunity to make a main memory request. Memory operations that have missed are indicated by a miss bit being set, so that the mechanism which selects memory operations to access the data cache may ignore them until they become non-speculative.

Load/store unit implementing non-blocking loads for a superscalar

A method of generating pure and decaying sinusoidal waveforms is readily implemented on arithmetic processors found in telecommunications circuits. The method is based on finite-difference equations and provides a sequence of signals having a high degree of spectral accuracy compared with presently-used methods. The sequence of signals can be generated in real-time without templates (ROM-stored patterns) because the method requires only two multiplications (16,18) and one addition (12) for each signal value generated in the sequence. The method finds application in dual-tone, multi-frequency (DTMF) telephone dialing systems.

Digital tone generation based on difference equations

A pulse generator for generating an output pulse which is synchronized to an internal clock pulse includes a detector latch circuit (24), a master latch (12), a clocked latch (14), a first clocked half-latch (16), and an output logic circuit (18). Th detector latch (24) is responsive only to the positive edge of the asynchronous pulse of a varying width for generating a trigger signal which is latched to a low logic level. The master latch (12) is responsive to the trigger signal for generating a first latched signal which is latched to a high logic level. The clocked latch means (14) is responsive to the first latched signal and a first internal clock pulse signal for generating a second latched signal which is latched to a high logic level. The first clocked half-latch (16) is responsive to the second latched signal and a second internal clock pulse signal for generating a control signal. The output logic circuit (18) is responsive to the first internal clock pulse signal and the control signal for generating an output pulse signal which is synchronized to the first internal clock pulse signal when the control signal is at a low logic level. A clearing circuit (19) is provided and is responsive to the control signal and the first internal clock pulse signal for generating a clearing signal which resets the first latched signal to a low logic level at the output of the master latch.

Positive edge triggered synchronized pulse generator

A method for operating an apparatus for facilitating communications between an analog device and a digital device, which apparatus includes a plurality of signal processing circuits and a control circuit for controlling the signal processing circuits. Each of the signal processing circuits includes signal attenuators and signal burst discrimination circuitry. The apparatus is operable in a plurality of stable states, preferably in an idle stable state, a transmit stable state, and a receive stable state. The apparatus also is operable in a plurality of transitional states, including up-transition states and down-transition states. The method includes the steps of evaluating each of the signal processing circuits by the signal burst discrimination circuitry, responding to detection of a burst indicator by setting a state indicator to an appropriate up-transition state, incrementally adjusting the attenuators in the signal processing circuits to enhance performance of the apparatus until the attenuators are at predetermined settings, periodically checking for presence of the burst indicator, on detection of cessation of the burst indicator, setting the state indicator to an appropriate down-transition state, incrementally adjusting the attenuators to redistribute attenuation losses among the signal processing circuits, if no burst indicator is detected, continuing such redistribution until the apparatus returns to the idle stable state.

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Austin, TX, United States of America

Rajiv M Hattangadi