Altera Corporation

Rajiv Kumar

Wei Yee Koay

Kuan Cheng Tang

Ting Lu

Ka Bo Wong

Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be precharged after an addressing decoding operation and in parallel with the evaluation phase. In either arrangement, a substantial amount of leakage and active power can be reduced.

Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration

Integrated circuits with memory elements are provided. In particular, a group of random-access memory cells may be coupled to first and second data lines via corresponding access transistors. One of the first and second data lines can be driven to a ground voltage level to write a zero or one into a selected memory cell in the group. A first dummy data line can be formed adjacent to the first data line, whereas a second dummy data line can be formed adjacent to the second data line. During data loading operations, at least one of the dummy data lines can be pulsed to temporarily drive the voltage on the associated data line to below the ground voltage level. Operated in this way, the write operation of the memory cells can be improved.

Memory element write-assist circuitry with dummy bit lines

Test circuitry for providing security in an integrated circuit includes a control circuit and a test power-on-reset circuit. The control circuit determines whether the integrated circuit is configured in a non-secure condition, and that generates a control signal in response to the non-secure condition. Accordingly, the test power-on-reset circuit selectively disables a power-on-reset circuit on the integrated circuit in response the control signal during test operations. The test power-on-reset circuit receives control instructions from the control circuit, and produces a test power-on-reset output according to the control instructions. The integrated circuit includes a logic gate that receives the test power-on-reset output and a power-on-reset signal from the power-on-reset circuit and generates an output signal for bypassing operations of the power-on-reset circuit on the integrated circuit.

Apparatus and method for security in an integrated circuit

Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port. The cross-coupled inverters in each memory cell may have a positive power supply terminal. The positive power supply terminal of each memory cell along a given column in the array may be coupled to a corresponding pull-up transistor. The pull-up transistor may receive a control signal from a pull-up weakening control circuit. The control signal may be temporarily elevated during write operations and may otherwise be driven back down to ground to help optimize read performance. The pull-up weakening control circuit may be implemented using a chain of n-channel transistors or a resistor chain.

Memory elements with dynamic pull-up weakening write assist circuitry

An array of memory cells on an integrated circuit device includes a plurality of memory cells arranged in at least one column. Each of the memory cells includes a plurality of transistors forming two complementary memory nodes. Each of the complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, which are connected in series and have a shared node between them. For a particular one of the memory cells, one of the shared nodes associated with one of the complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of the memory cells, and another of the shared nodes associated with another of the complementary memory nodes is directly connected to a corresponding shared node associated with a corresponding complementary memory node in a third one of the memory cells.

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Penang, Malaysia

Rajiv Kumar