Real Intent, Inc.

Hewlett-packard Company

Rajiv Kumar

Prakash Narain

John Mark Beardslee

Christopher F Morrison

Rajeev Kumar Ranjan

Paul S Chan

Carl D Burch

A method and apparatus are described that facilitate validation of a hardware design having multiple hierarchical levels. In one embodiment, a representation of the hardware design is received, and the hardware design is validated by performing validation processing on a plurality of sub-problems. Each of the plurality of sub-problems covers a computationally feasible size of the hardware design at a corresponding hierarchical level. In another embodiment, validation of a hardware design includes making use of validation processing previously performed with respect to one or more modules included in the hardware design based on the hierarchical relationship between these modules and other modules included in the hardware design.

Hierarchical functional verification

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, hardware design defects can be detected using a novel Intent-Driven Verification process. First, a representation of a hardware design and information regarding the intended flow of logical signals among variables in the representation are received. Then, the existence of potential errors in the hardware design may be inferred based upon the information regarding the intended flow of logical signals by (1) translating the information regarding the intended flow of logical signals into a comprehensive set of checks that must hold true in order for the hardware design to operate in accordance with the intended flow of logical signals, and (2) determining if any of the checks can be violated during operation of circuitry represented by the hardware design.

Intent-driven functional verification of digital designs

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a method is provided for explicitly associating state information with variables of a language description of a hardware design. Information regarding the intended flow of logical signals among the variables, which represent interconnects in the hardware design through with the logical signals pass, is received. Then, the intended flow of logical signals is modeled by associating state information with the variables in accordance with the intended flow of logical signals. Advantageously, in this manner, the integrity of the data flow can be verified by confirming checks that are expressed as a function of the states associated with the variables.

Modeling and verifying the intended flow of logical signals in a hardware design

A method of operating a digital computer to provide instrumentation data for a shared library running in an environment in which programs are loaded and unloaded by a loader. The environment supports the operation of at least one program in addition to the shared library, the program utilizing at least one function provided by the shared library. The operating environment includes storage for a predetermined environment variable that may be read by any program running in the environment. The method includes the steps of causing the loader to examine the environment to determine if the predetermined environment variable has been set; and storing profile based optimization data stored in the shared library code in a location specified by the predetermined environmental variable if the predetermined environmental variable was present in response to a command being sent to the loader. The profile based optimization data is normally stored when the shared library is unloaded from the operating environment by the loader.

Profile based optimization of shared libraries

An improved compilation and linkage system for use in operating a computer to generate a cross-module optimized executable code file from a plurality of source files and object files. The source files are compiled to intermediate code files using a compiler sub-system. In the preferred embodiment of the present invention, the intermediate code files consist of intermediate language instructions that can be optimized for execution on a predetermined computer and a global symbol table. The compiler sub-system can also be used to generate conventional object code files if desired. A linkage sub-system is then used to cross-module optimize the code in a plurality of intermediate code files and link the resultant object code with any other object code files to generate the executable code file for execution on the computer in question. To the programmer, the operation of the compiler and linkage sub-systems of the present invention is essentially indistinguishable from that of a conventional compiler and linkage sub-system that lacks cross-module optimization.

Growing community of inventors

Santa Clara, CA, United States of America

Rajiv Kumar