Marvell International Limited

Other

Intel Corporation

Texas Instruments Corporation

Rajith Kumar Mavila

Bradley C Aldrich

Vasudev Bibikar

Mark Norman Fullerton

Vinod J Menezes

Nancy G Woodbridge

Amit Dor

Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.

Techniques for putting platform subsystems into a lower power state in parallel

A device for capturing image data includes a first image sensor. A first interface receives the image data from the first image sensor based on a first synchronization signal. The first interface has a first mode that is associated with receiving the first synchronization signal from the first image sensor and a second mode that is associated with sending the first synchronization signal to the first image sensor.

Image sensor interface

An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.

Frequency-dependent voltage control in digital logic

A system includes an image sensor and an interface to receive image data from the image sensor. The interface selects between providing at least one synchronization signal to the image sensor and receiving the synchronization signal(s) from the image sensor. The synchronization signal(s) are associated with the communication of the image data from the image sensor.

A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slower clock signal and provided to an AND gate gating the slower clock signal based on the value of a select signal formed by the synchronized sleep signal. The slower clock signal is delayed by a number of faster clock cycles equal to the time taken by the select signal to be received at the AND gate after the sleep signal is synchronized to the slower clock signal. In an alternative embodiment, a signal control block ensures that the 0 to 1 transition on one of the select signals follows the 1 to 0 transition on another select signal when the value of the sleep signal changes. In addition, each select signal is synchronized with a negative edge of the corresponding clock signal selected.

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Austin, TX, United States of America

Rajith Kumar Mavila