Gradient Design Automation Inc.

Qualcomm Incorporated

Advanced Micro Devices Corporation

Moscape, Inc.

Rajit Chandra

Adi Srinivasan

Rajat Mittal

Madan Krishnappa

Mohammad Tamjidi

Peng Li

Larry Pileggi

Mehdi Asheghi

John Yanjiang Shu

Paolo Carnevali

Martin Saint-Laurent

Mehdi Saeidi

Niladri Mojumder

Ronald Alton

Lucio Lanza

Ali Akbar Merrikh

Mohamed Waleed Allam

Melika Roshandell

Sachin Dileep Dasnurkar

Tao Xue

Daniel Rubin

Chandrasekhara Somanathan

Mohammad Ghasemazar

Joydeep Mitra

Nanda Gopal

Steven B Parks

An apparatus is disclosed. The apparatus includes a circuit, a conductor interconnecting a portion of the circuit, and a processor configured to determine a temperature of the conductor and adjust at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The at least one parameter includes a lifetime estimate for the conductor. A method of operating an apparatus including a circuit and a conductor interconnecting a portion of the circuit is disclosed. The method includes determining a temperature of the conductor, and adjusting at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The parameter includes a lifetime estimate for the conductor.

Method and apparatus for integrated circuit monitoring and prevention of electromigration failure

An apparatus is presented. The apparatus includes a first circuit configured to predict temperatures of a location for a plurality of time instances based on measured temperatures and a second circuit configured to schedule a thermal mitigation function based on the predicted temperatures. A method of operating an apparatus is presented. The method includes measuring temperatures on an integrated circuit, predicting temperatures of a location for a plurality of time instances based on the measured temperatures, and scheduling a thermal mitigation function based on the predicted temperatures. An apparatus is presented. The apparatus includes means for measuring temperatures on an integrated circuit, means for predicting temperatures of a location for a plurality of time instances based on measured temperatures, and means for scheduling a thermal mitigation function based on the predicted temperatures.

Thermal mitigation based on predicted temperatures

A temperature sensor position offset error correction power implementation include monitors (e.g., digital power monitor/meter) to measure activity on a die, and uses the activity measurements to compute real-time temperature offsets by converting activity to power, which can be used in a simplified compact thermal model. A system on chip including the die receives a temperature measurement of a region of the system on chip from a sensor. Power consumed by the region is estimated based on the measured activity, and temperature measurement of the system on chip is adjusted based on the estimated power.

Temporal temperature sensor position offset error correction

A thermal controller for managing thermal energy of a multi-core processor is provided. The cores include a first core processing a load and remaining cores. The thermal controller is configured to determine that a temperature of the first core is greater than a first threshold, determine a temperature of a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold, and determine whether the temperature of the second core is greater than or less than a second threshold. The thermal controller is configured to transfer at least a portion of the load of the first core to the second core in response to determining that the temperature of the first core is greater than the first threshold and based on whether the temperature of the second core is greater than or less than the second threshold.

Thermal mitigation of multi-core processor

A method, an apparatus, and a computer program product are provided. The apparatus may be a UE. The UE has a processor including a plurality of cores. The plurality of cores includes a first core and remaining cores. The UE determines a temperature of the first core of the plurality of cores. The first core processes a load. The UE determines that the temperature of the first core is greater than a first threshold. The UE determines that the temperature of the first core is not greater than a second threshold. The second threshold is greater than the first threshold. The UE transfers at least a portion of the load of the first core to a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold.

Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power

A method and apparatus generates thermal partitions for metal interconnects of an integrated circuit, based on interconnect self heat data and mutual heat data. Each of the thermal partitions includes data identifying thermally related interconnects and respective temperature values associated with each of the thermally related interconnects. Thermally related partitions that can be computed efficiently and simultaneously and the results then integrated using superposition for the full chips.

Method and apparatus for improved integrated circuit temperature evaluation and IC design

A thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain static and/or transient thermal simulations of the chips based on thermal models and boundary conditions. The thermal simulations are performed in accordance with one or more grids, with boundaries and/or resolutions being determined by adaptive and/or hierarchical multi-dimensional techniques. The adaptive grid techniques include material-boundary, rate-of-change, and convergence-information heuristics. For example, a finer grid is used in a region having higher temperature gradients compared to a region having lower temperature gradients. The hierarchical grid techniques are based on critical, intermediate, and boundary regions specified manually or automatically, each region having a respective grid resolution. For example, a critical region is analyzed according to a grid that is finer than a grid of an intermediate region, and resolution of a grid of a boundary region is adapted to boundary conditions.

Thermal simulation using adaptive 3D and hierarchical grid mechanisms

A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.

Method and apparatus for thermal modeling and analysis of semiconductor chip designs

Transient thermal simulation of semiconductor chips uses region-wise variable spatial grids and variable temporal intervals, enabling spatio-temporal thermal analysis of semiconductor chips. Temperature rates of change across a die and/or package of an integrated circuit are computed and tracked versus time. Critical time interval(s) for temperature evaluation are determined. Temperatures of elements, components, devices, and interconnects are updated based on a 3D full chip temperature analysis. Respective power dissipations are updated, as a function of the temperatures, with an automated interface to one or more circuit simulation tools. Subsequently new temperatures are determined as a function of the power dissipations. User definable control and observation parameters enable flexible and efficient transient thermal analysis. The parameters relate to power sources, monitoring, reporting, error tolerances, and output snapshots. Viewing of waveform plots and 3D spatial variations of temperature enable efficient communication of results of the thermal analysis with designers of integrated circuits.

Transient thermal analysis

In a first variation, a thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain thermal simulations of the chips based on thermal models and boundary conditions. The suite uses results of the simulations to modify thermally significant structures to achieve desired thermal variations across a chip, meet design assertions on selected portions of the chip, and verify overall performance and reliability of the chip over designated operating ranges and manufacturing variations. In a second variation, a discretization approach models chip temperature distributions using heuristics to adaptively grid space in three dimensions. Adaptive and locally variable grid spacing techniques are used to efficiently and accurately converge for steady state and/or transient temperature solutions. The modeling optionally reads a mesh initialization file specifying selected aspects and parameters associated with controlling use and behavior of the variable grid spacing techniques.

Thermally aware design modification

A method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities is provided. One embodiment of a novel method for performing performance analysis of a semiconductor chip design includes receiving at least one input calculated in accordance with an actual (e.g., purposefully calculated rather than assumed or estimated) temperature of a semiconductor device and/or an interconnects in the semiconductor ship design. This input is then used to assess at least one temperature-dependent performance parameter of the semiconductor chip design.

Method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities

A method and apparatus for full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal analysis of a semiconductor chip design comprises receiving at least one input relating to a semiconductor chip design to be analyzed. The input is then processed to produce a three-dimensional thermal model of the semiconductor chip design. In another embodiment, thermal analysis of the semiconductor chip design is performed by calculating power dissipated by transistors and interconnects included in the semiconductor chip design and distributing power dissipated by the interconnects.

Method and apparatus for full-chip thermal analysis of semiconductor chip designs

A thermally aware design automation suite integrates system-level thermal awareness into the design of semiconductor chips. A thermal analysis engine performs fine-grain thermal simulations of the semiconductor chip based on thermal models and boundary conditions for all thermally significant structures in the chip and the adjacent system that impact the temperature of the semiconductor chip. The thermally aware design automation suite uses the simulations of the thermal analysis engine to repair or otherwise modify the thermally significant structures to equalize temperature variations across the chip, impose specified design assertions on selected portions of the chip, and verify overall chip performance and reliability over designated operating ranges and manufacturing variations. The thermally significant structures are introduced or modified via one or more of: change in number, change in location, and change in material properties.

Semiconductor chip design having thermal awareness across multiple sub-system domains

A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor chip design such that the thermal gradient is normalized by heat dissipated by the supplemental heat source.

Growing community of inventors

Cupertino, CA, United States of America

Rajit Chandra