Institute of Microelectronics

Oki Techno Centre Pte Ltd.

Agency for Science, Technology and Research

Ftd Solutions Pte., Ltd.

Rajinder Singh

Junichi Shibata

Kai Tuan Yan

Xuesong Chen

Wooi Gan Yeoh

Pradeep Basappa Khannur

Hiroshi Nakamura

Au Yeung On

Ding Yong

A radio frequency identification transceiver is disclosed. The radio frequency identification transceiver includes: a transmitter path, including; a pulse shaper to tunably shape the pulse of a signal to be transmitted in different predefined frequency ranges; a modulator to modulate the shaped pulse to be transmitted into one of a plurality of predefined frequency ranges; a receiver path, including: a demodulator to demodulate a received signal from a plurality of predefined frequency ranges.

Radio frequency identification transceiver

A clock and data recovery circuit has a voltage controlled oscillator that provides a clocking signal synchronized to a received serialized data. A multiple phase generator converts the clocking signal to a plurality of multiple phased clocking signals. A data capture device acquires the serialized data with each of the plurality of multiple phased clocking signals to create multiple phased data signals. A phase detector determines if the clocking signal is in phase with the recovered serialized data and providing a lead signal and a lag signal indicating whether the clocking signal is in phase with the recovered serialized data. A frequency initializing device assists acquisition of lock of the voltage controlled oscillator to a reference clock signal. A recovered data selector selects which of the multiple phased data signals are to be transferred to external circuitry for further processing.

Single-VCO CDR for TMDS data at gigabit rate

Methods and structures are disclosed which realize high Q inductors to provide on-chip noise matching of microwave monolithic integrated circuits, such as low noise amplifiers and output matching networks for power amplifiers. High Q inductors, of typically 6nH, are devised by using the inductance of package leads, bondwires, electronic board trace wires and transmission lines and other components in various configurations. These and other components are serially connected starting from a chip pad, representing a circuit node, to a circuit input on a that electronic board.

High Q inductor realization for use in MMIC circuits

A bias stabilization circuit for biasing the DC gate bias of a stabilized transistor is disclosed. The bias stabilization circuit may be comprised of a bias transistor that is fabricated concurrent with, and on the same chip as, the stabilized transistor. Preferably, the bias transistor and the stabilized transistor are fabricated physically close to each other and during the same process so that the electrical characteristics of the transistors are closely related. In a preferred embodiment, a drain of the bias transistor is connected to a load comprising a first resistor, a second resistor, and a third resistor. The drain of the bias transistor is connected through the third resistor to a junction between the first and second resistors. The first and second resistors are connected in series between a first supply potential and a reference potential. The gate and source of the bias transistor are connected together through a fourth resistor. The gate is also connected to a second supply potential that is derived from the first supply potential. The third and fourth resistors are fabricated together with the bias and stabilized transistors. By this configuration, if the operating characteristics of the stabilized transistor varies from chip to chip during fabrication due to process variations, or the supply potentials vary, the bias transistor will compensate to maintain a substantially constant operating point of the stabilized transistor.

Bias stabilization circuit

Growing community of inventors

Singapore, Singapore

Rajinder Singh