Texas Instruments Corporation

Motorola Corporation

Rajesh Tiwari

Suresh Venkatesan

Janos Farkas

Venkat Kolagunta

Mohammed Rabiul Islam

Brian George Anthony

John Mendonca

Abbas Guvenilir

Nital S Patel

Thomas Dyer Bonifield

Jiong-Ping Lu

Brian Keith Kirkpatrick

Jeff A West

Andrew Tae Kim

Scott Alexander Johannesmeyer

Russell Duane Fields

David Permana

Brock W Fairchild

Chris M Bowles

Scott A Boddicker

Albert Cheng

A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.

Die having coefficient of thermal expansion graded layer

A trench is formed in a low K dielectric () over a plurality of vias () also formed in the low K dielectric layer (). The vias are separated by a distance of less than Xand the edge of the trench is greater than Xfrom the edge &#x3b1; of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (), () to form the interconnect line.

Dual depth trench termination method for improving Cu-based interconnect integrity

The present invention defines a system () for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization. The system has a CMP system () that performs copper overpolish and barrier polish on a copper-based semiconductor wafer (). A profilometer () measures actual dishing occurring in the copper metallization after polishing. An input data set () includes a dishing target for the semiconductor wafer. A data integrity function () evaluates the profilometer's measurement, and generates an indicator of the reliability of the measurement. A modeling function () receives the measurement, the indicator, and the dishing target, and evaluates any differential between the dishing target and actual dishing. The modeling function generates a processing target to eliminate the differential, and modifies this process responsive to the indicator. A processing control function () receives the processing target, and alters the copper overpolish or barrier polish responsive to the processing target.

Versatile system for controlling semiconductor topography

The present invention defines a versatile system for analyzing accuracy of industrial measurement data. The system of the present invention compiles measurements of a primary device characteristic from a representative cross-section of a population of devices. The system provides a modeling function, from which is determined a variance for each measurement&#x2014;forming a corresponding compilation of variances (). The compilation of variances is evaluated for discontinuities (), to identify a discontinuity within the compilation of variances. This discontinuity is utilized to determine a demarcation () between accurate and inaccurate measurement data.

Versatile system for variance-based data analysis

A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.

Method of preventing seam defects in isolated lines

A copper interconnect polishing process begins by polishing ( ) a bulk thickness of copper ( ) using a first platen. A second platen is then used to remove ( ) a thin remaining interfacial copper layer to expose a barrier film ( ). Computer control ( ) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed ( ) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier ( ) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations ( ). A scrubbing operation ( ) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process

A copper interconnect polishing process begins by polishing (,) a bulk thickness of copper (,) using a first platen. A second platen is then used to remove (,) a thin remaining interfacial copper layer to expose a barrier film (,). Computer control (,) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (,) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (,) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (,). A scrubbing operation (,) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scrubber.

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Plano, TX, United States of America

Rajesh Tiwari