Dxcorr Design Inc.

Rajesh Tiruvuru

Sagar V Reddy

Manish Agarwal

Nirmalya Ghosh

A voltage stacked system that includes a stack of near threshold computing (NTC) chips for achieving inter-chip communication with simple wires as interconnections is disclosed. The chips include at least two secondary supply voltages and at least a secondary ground voltage electrically coupled to the stack of the chips arranged in series. The secondary supply and ground voltages are tapped in a predefined sequence at one or more predefined access points in the stack to generate two versions of an internal voltage within each of the chips. Each of the two versions of the internal voltage is a voltage difference between respective supply voltages and ground voltages, and the two have a set voltage shift such that the chips in the stack have supply voltages overlapping with those in the neighboring chips. Optionally, the two voltages are boosted to further higher voltages as needed using charge pumps.

Inter-chip input-output (IO) for voltage-stacked near threshold computing (NTC) chips

An electronic biasing circuit for memory operating in a high temperature environment, comprising a first memory cell and a second memory cell, a first MOSFET transistor electrically coupled in series with the first memory cell, wherein the first MOSFET transistor is configured as a switch, a second MOSFET transistor electrically coupled in series with the second memory cell, wherein the second MOSFET transistor is configured as a switch, a DC bias current source configured to generate a negative DC bias voltage signal, a first read/word line electrically coupled to a gate of the first MOSFET transistor, and a second read/word line electrically coupled to a gate of the second MOSFET transistor, wherein in response to a read operation of the first memory cell, the second read/word line is configured to deliver the negative DC bias voltage signal to the gate of the second MOSFET transistor.

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Bengaluru, India

Rajesh Tiruvuru