Intel Corporation

Rajesh S Parthasarathy

Gilbert A Neiger

Martin Guy Dixon

Robert S Chappell

Keshavan K Tiruvallur

Jason W Brandt

James B Crossland

Luke Hood

Shivnandan D Kaushik

Frank Binns

Robert Valentine

Mark Jay Charney

Bret L Toll

Mohan J Kumar

Christopher J Hughes

Jesus Corbal

Richard A Uhlig

Milind Baburao Girkar

Robert Charles Swanson

Mahesh S Natu

Srinivas Chennupaty

Matthew C Merten

Dion Rodgers

Ravi Rajwar

Jonathan Cannon Hall

Chris J Newburn

Mark J Buxton

Peter Lachner

Baskaran Ganesan

Thanunathan Rangarajan

David W Burns

Hermann Gartler

Vijaykumar Balaram Kadgi

Jeffrey G Wiedemeier

Gautam Doshi

Mayank Bomb

Madhavan Parthasarathy

Michael D Tucknott

John Faistl

Yen-Kuang (y K) Chen

Hideki (Saito) Ido

Rajesh Nagaraja Murthy

Andrew V Anderson

Steven M Bennett

Konrad K Lai

Sridhar Muthrasanallur

Alexandre J Farcy

Shamanna M Datta

Ilhyun Kim

Prakash Math

Glenn J Hinton

Raj K Ramanujan

Robert J Greiner

Jeremy J Shrall

Erik C Cota-Robles

David Zimmerman

Xiang Chris Zou

Patrice L Roussel

Sebastian Schoenberg

Stalinselvaraj Jeyasingh

Lawrence O Smith

Rajesh Sankaran Madukkarumukumana

Sanjoy K Mondal

Sham M Datta

Adrian C Moga

Muthukumar Swaminathan

Wayne Alan Downer

Larry O Smith

Alain Kägi

Christine E Wang

Scott J Cape

Aravindh Bakthavathsalu

Shammanna M Datta

Shivnanda Kaushik

Wayne A Downer

Stalinselvaraj Jayasingh

A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

Method and apparatus for bus lock assistance

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

Gathering and scattering multiple data elements

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Providing state storage in a processor for system management mode

A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.

Method and apparatus for continued retirement during commit of a speculative region of code

Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Technique for communicating interrupts in a computer system

In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

Apparatus, method, and system for implementing micro page tables

In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed.

Controlling time stamp counter (TSC) offsets for mulitple cores and threads

Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode

Growing community of inventors

Hillsboro, OR, United States of America

Rajesh S Parthasarathy