Semiconductor Components Industries, LLC

Rajesh S Nair

Zia Hossain

Takeshi Ishiguro

Shanghui Larry Tu

Gennadiy Nemtsev

Yingping Zheng

Mohammed Tanvir Quddus

James Adams

Mohamed Imam

Hui Wang

An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.

Method of forming an EPROM cell and structure therefor

A lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches bounding in part a multiplicity of striped doped regions having opposite or alternating conductivity types.

Semiconductor structure with improved on resistance and breakdown voltage performance

In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.

High voltage lateral FET structure with improved on resistance performance

In one embodiment, a lateral FET structure () is formed in a body of semiconductor material (). The structure () includes a plurality non-interdigitated drain regions () that are coupled together with a conductive layer (), and a plurality of source regions () that are coupled together with a different conductive layer (). One or more interlayer dielectrics () separate the two conductive layers (). The individual source regions () are absent small radius fingertip regions.

Lateral FET structure with improved blocking voltage and on resistance performance and method

A transistor () is formed as a matrix of transistor cells () that have drain metal strips () for contacting drains () of the transistor cells and source metal strips () for contacting sources () of the transistor cells. An interconnect layer () overlying the matrix of transistor cells has first portions () that contact one the drain metal strips with first and second vias () and second portions () that contact one of the source metal strips with third and fourth vias ().

Semiconductor power device having a diamond shaped metal interconnect scheme

A semiconductor device ( ) is formed to have a well ( ) in a substrate ( ). The well and the substrate have the same doping type, for example both P-type or both N-type. Low resistance contact regions ( ) of a second conductivity type are formed to at least abut the well. A drain ( ) is formed within one low resistance contact region. A source ( ) is formed in the substrate and laterally displaced from the other low resistance contact region. A buried layer ( ) is formed laterally across the well.

Method of forming a semiconductor device and structure therefor

A method of forming a semiconductor device ( ) forms a plurality of P and N stripes ( ) within a first region ( ) that is formed with an opposite conductivity to a substrate ( ). The plurality of P and N stripes assist in providing a low on-resistance. A portion ( ) of the first region underlies the P and N stripes and protects the semiconductor device from high voltages applied to the drain. A base layer ( ) and a cap layer ( ) further reduce the on-resistance of the semiconductor device.

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Chandler, AZ, United States of America

Rajesh S Nair