Cisco Technology, Inc.

Cisco Systems Inc.

Rajesh Patil

Harish Ramamurthy Devanagondi

Harshvardhan P Sharangpani

Hugh Barrass

Judge K Arora

Manoj Khare

Kent G Fielden

David M Smith

Sanjeev Mahalawat

Adam Goldstein

Kamran Torabi

Jianyong Sun

Harshvardan Sharangpani

Judge Kennedy Arora

Judge Kennedy Cisco Systems Inc Arora

A network switch having a hybrid switch architecture, which is scalable to increase connectivity, buffering, and bandwidth by using multiple shared-memory switch fabrics and multiple crossbar switch fabrics. Each of the crossbar switch fabrics is coupled to each of the shared-memory switch fabrics. The shared-memory switch fabrics are configured to store and retrieve packets. The crossbar switch fabrics are configured to distribute and recollect packets to and from each of the shared-memory switch fabrics. The network switch having a hybrid switch architecture distributes packets from a crossbar switch fabric to the multiple shared-memory switch fabrics to share the distributed packets among the multiple shared-memory switch fabrics.

Network switch having a hybrid switch architecture

A system, method and tangible medium for unified exception handling with distributed exception identification includes a packet processing pipeline with at least two processing stages for processing data packets, each of the data packets being processed having an associated exception map in a memory of the apparatus. An exception detector at each processing stage detects whether any exception conditions apply to the data packet at the processing stage, and if so, a bit setter sets, modifies, or resets one or more bits in the exception map associated with exception conditions detected at the processing stage. An exception handler processes the exception map in response to the state of in the exception map after all the processing stages are complete.

Method and apparatus for unified exception handling with distributed exception identification

A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer, and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.

Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data

A method and apparatus is disclosed herein for a rule processor for conducting contextual searches, the processor comprising a plurality of input payload search registers, search execution engine coupled to the plurality of search registers to perform one or more contextual searches on content in the search registers by via parallel pattern matching in response to executing rules specifying the one or more searches, and presenting one or more patterns to the content in the search registers.

Programmable rule processing apparatus for conducting high speed contextual searches and characterizations of patterns in data

Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.

Methods and apparatuses for evaluation of regular expressions of arbitrary size

A network switch having a hybrid switch architecture, which is scalable to increase connectivity, buffering, and bandwidth by using multiple shared-memory switch fabrics and multiple crossbar switch fabrics. Each of the crossbar switch fabrics is coupled to each of the shared-memory switch fabrics. The shared-memory switch fabrics are configured to store and retrieve packets. The crossbar switch fabrics are configured to distribute and re-collect packets to and from each of the shared-memory switch fabrics. The network switch having a hybrid switch architecture distributes packets from a crossbar switch fabric to the multiple shared-memory switch fabrics to share the distributed packets among the multiple shared-memory switch fabrics.

Unified exception handling may be provided by processing a data packet through at least two pipelined processing stages in a data packet processor such as a switch, router, bridge, or similar network device, each of the data packets having associated with it (while it is being processed) an exception map disposed in a memory of the network device. The bits in the exception map are set, modified, or reset in response to exception conditions detected at the various processing stages. After the packet has been fully processed, an exception handler takes as an input the exception map and further processes the packet in response to the state of the exception map.

Growing community of inventors

Santa Clara, CA, United States of America

Rajesh Patil