Juniper Networks, Inc.

Gigafin Networks, Inc.

Fungible, Inc.

Rajesh Nair

Jean-Marc Frailong

Jeffrey Glenn Libby

John Keen

Sharada Yeluri

Pradeep S Sindhu

Kevin J Rowett

Somsubhra Sikdar

Jianhui Huang

Komal Rathi

Jian Hui Huang

Wael Noureddine

Avanindra Godbole

Anurag P Gupta

Felix A Marti

Aibing Zhou

Hoai Vu Thanh Tran

Aravind Vidhyasagar Lappasi

Leith Alan Leedom

Dmitriy Leonidovich Budko

Gaurav Gupte

Techniques are described for providing a scaled-out transport supported by interconnected data processing units (DPUs) that operates as a single system bus connection proxy for device-to-device communications within a data center. As one example, this disclosure describes techniques for providing a Peripheral Component Interconnect Express (PCIe) proxy for device-to-device communications employing the PCIe standard. The disclosed techniques include adding PCIe proxy logic on top of a host unit of a DPU to expose a PCIe proxy model to application processors, storage devices, network interface controllers, field programmable gate arrays, or other PCIe endpoint devices. The PCIe proxy model may be implemented as a physically distributed Ethernet-based switch fabric with PCIe proxy logic at the edge and fronting the PCIe endpoint devices. The interconnected DPUs and the distributed Ethernet-based switch fabric together provide a reliable, low-latency, and scaled-out transport that operates as a PCIe proxy.

Scaled-out transport as connection proxy for device-to-device communications

A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component.

Efficient arithimetic logic units

A device may emulate target instructions by executing a first set of microinstructions, and may store a base address of a table that includes a microinstruction provided in a second set of microinstructions for emulating the target instructions. The device may also locate the microinstruction based on the stored base address, and emulate one of the target instructions by executing the microinstruction.

Emulation of multiple instruction sets

Efficient arithmetic logic units

Methods and systems consistent with the present invention provide efficient packet replication in a router in order to multicast a stream of data. Packets are replicated and processed in a multithreaded environment. Embodiments consistent with the present invention implement a two-stage process for packet replication. The first stage thread will recirculate the packet to multiple second-stage threads. These second-stage threads will then create one or more outgoing copies of the packet. In this way, the copies are handled by multiple threads running in parallel.

System and method for efficient packet replication

A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to extract read and write addressing from the nexthop instruction instead of performing this operation in microcode. A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to compare a nexthop read address to a special value and to indicate whether the nexthop read address matches the special value, instead of performing this operation in microcode. A method for determining a network address by performing a single extraction of bit fields of a tree instruction to allow multiple tree search processes to be performed.

Hardware support for instruction set emulation

A devices and method for parsing a data stream comprises a parser stack configured to store one or more parsing symbols, each parsing symbol representing a different state of data stream parsing, a table interface configured to retrieve one or more production rules from a production rule table according to the parsing symbols, and a state machine configured to control the parsing of a data stream according to the retrieved production rules.

Symbol parsing architecture

A system and method for parsing a data stream comprises a production rule table populated with production rules, a parser table populated with production rule codes that correspond to production rules within the production rule table, and a direct execution parser to identify production rule codes in the parser table and to retrieve production rules from the production rule table according to the identified production rule codes, the direct execution parser is operable to parse a data stream according to the retrieved production rules.

Parser table/production rule table configuration using CAM and SRAM

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Fremont, CA, United States of America

Rajesh Nair