Intel Corporation

Rajesh Nagaraja Murthy

Mohan J Kumar

Robert Charles Swanson

Mahesh S Natu

Rajesh S Parthasarathy

Frank Binns

Baskaran Ganesan

Thanunathan Rangarajan

Gautam Doshi

Shamanna M Datta

Shammanna M Datta

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Providing state storage in a processor for system management mode

Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM

Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode

Growing community of inventors

Bengaluru, India

Rajesh Nagaraja Murthy