University of California

Rajesh Kumar Gupta

Nikil Dutt

Yuvraj Agarwal

Sumit Gupta

Alexandru Nicolau

Zeyu Chen

Jeng-Hau Lin

Zhuowen Tu

Yunfan Yang

Disclosed are devices, systems and methods for providing efficient implementations for pattern recognition. Embodiments of the disclosed technology use local binary comparisons and random projection in place of conventional convolution operations. Some embodiments of the disclosed technology provide an important means to improve memory and speed efficiency that is particularly suited for small footprint devices and hardware accelerators. Other embodiments compare a binary pattern to one or more portions of an input image to determine a plurality of binary results, and generate an estimate of the feature based on the plurality of binary results. Yet other embodiments generate an final image, comprising a final estimate of the feature, by randomly selecting one or more portions from each of a plurality of initial images, wherein each of the plurality of initial images comprises an initial estimate of the feature.

Local binary pattern networks methods and systems

This application includes systems and techniques that permit computers to remain accessible while in a low-power mode. In some implementations, the technique includes receiving at a first computer, via a computer network, information regarding a second computer transitioning to a low-power mode of operation; receiving at the first computer network communications designated for the second computer; processing at the first computer at least a portion of the network communications on behalf of the second computer without transitioning the second computer out of the low-power mode of operation, where the processing comprises processing the at least a portion of the network communications on behalf of the second computer within a virtual machine corresponding to the second computer; and initiating, via the computer network, a transition of the second computer out of the low-power mode of operation when at least one of the network communications satisfies a predetermined condition.

Architecture to enable energy savings in networked computers

A method for performing high-level synthesis (HLS) of a digital design includes a first phase for performing transformations on a behavioral description of the design, and a second phase for selecting a transformation from a plurality of transformations for transforming the behavioral description. The method further includes a third phase for implementing the transformed behavioral description using lower level primitives, and a fourth phase for generating implementation codes for the design.

Method and apparatus for designing circuits using high-level synthesis

Growing community of inventors

San Diego, CA, United States of America

Rajesh Kumar Gupta