Marvell International Limited

Lsi Corporation

Lsi Logic Corporation

Rajesh Juluri

Yanni Chen

Cheng Qian

Joonsang Choi

Josselin De La Broise

Deepak Jain

Li-Fu Jeng

Advait Madhav Mogre

Robert Morelos-Zaragoza

Chusong Xiao

Huan T Truong

Robert-Henry Morelos-Zaragoza

A coexistence system including a first transceiver module, an interface, a second transceiver module, and an arbitration module. The first transceiver module, in a first network device, is configured to generate at least one first request signal. The first transceiver module operates according to a first wireless communication standard. The at least one first request signal requests transmission or reception for the first transceiver module. The interface is configured to generate a first priority signal based on the at least one first request signal. The first priority signal indicates a first priority level of first data signals corresponding to the at least one first request signal. The second transceiver module, in the first network device, is configured to (i) generate at least one second request signal, and (ii) generate a second priority signal. The second transceiver module operates according to a second wireless communication standard. The at least one second request signal requests transmission or reception for the first transceiver module. The second priority signal indicates a second priority level of second data signals corresponding to the at least one second request signal. The arbitration module is configured to (i) based on the first priority level and the second priority level, arbitrate the at least one first request signal and the at least one second request signal, and (ii) based on the arbitration of the at least one first request signal and the at least one second request signal, selectively connect antennas to the first transceiver module and the second transceiver module in one of multiple configurations.

Method and apparatus for priority based coexistence arbitration

A discrete Fourier transform calculation apparatus includes a plurality of multiplier units, and a plurality of butterfly calculation units. Each butterfly calculation unit is configured to perform simultaneous calculations for at least two stages of a fast Fourier transform (FFT) algorithm by using shared resources of the butterfly calculation unit. Each butterfly calculation unit includes a respective memory device to store input data for the corresponding at least two stages of the FFT algorithm, and a respective butterfly calculator coupled to the respective memory device. Each butterfly calculation unit also includes a respective controller coupled to the respective memory device and the respective butterfly calculator. The respective controller is configured to control the corresponding butterfly calculation unit to calculate the corresponding at least two stages of the FFT algorithm. The plurality of butterfly calculation units and the plurality of multiplier units are coupled in series.

Discrete fourier transform calculation method and apparatus

A coexistence system including a first transceiver module in a first network device, generating a first request signal that requests transmission or reception for the first transceiver module, and operating according to a first wireless communication standard. An interface, based on the first request signal, generates a first priority signal, which indicates a first priority level of first data signals. A second transceiver module is in the first network device and generates a second request and priority signals. The second transceiver module operates according to a second wireless communication standard. The second request signal requests transmission or reception for the first transceiver module. The second priority signal indicates a second priority level of second data signals. An arbitration module (i) based on the first and second priority levels, arbitrates the first and second request signals, and (ii) based thereon, selectively connects antennas to the first and second transceiver modules.

In the various embodiments, decoders, methods, systems and devices exploit state information associated with transmitted packets to facilitate decoding operations. Specifically, in at least some embodiments, packets are received by a receiver. If the packet is unable to be decoded because of corruption, state information associated with that packet is buffered at the receiver and used for subsequent decoding. A retransmitted packet is then received, checked for corruption and, if not corrupted, is decoded leveraging the previously-buffered state information associated with the corrupted packet. In an event that one or more retransmitted packets are corrupted, this process can be repeated a number of times.

Use of previously buffered state information to decode in an hybrid automatic repeat request (H-ARQ) transmission mode

A high throughput and scalable MIMO detector can use a K-Best detection algorithm to find K combinations of transmit symbols that are likely to be the symbols that were actually transmitted. The K-best MIMO detector can include a plurality of stages, where each stage may correspond to a transmit antenna, and each stage can find K best symbol combinations based on information from a previous stage. To find the new K best symbol combinations, at each stage, a plurality of metrics for potential combinations are computed and sorted by magnitude. The MIMO detector preferably uses a high throughput, merge sorting algorithm to sort the metrics.

Apparatus and method for finding likely combinations of transmitted symbols

High-throughput pipelined and scalable architecture for a K-Best MIMO detector

Discrete Fourier transform calculation method and apparatus

Various decoders, methods, systems, and devices are provided that selectively employ a decoding operation as a function of the size of a received data packet. In at least some embodiments, a first decoding operation is performed on data packets within a first size range. A second decoding operation(s), different from the first, is (are) performed on data packets within a second size range. In at least some embodiments, the first decoding operation is a sliding-window decoding operation and the second decoding operation is one other than a sliding-window decoding operation.

Decoding operations in normal transmission mode

An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data in a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.

Unified memory architecture for recording applications

A method for modulating a video input signal received into a modulation circuit is disclosed. A first step of the method generally comprises (A) during a first modulation pass, generating (i) a primary frame by inserting a plurality of primary synchronization codes into the video input signal, (ii) a secondary frame by inserting a plurality of secondary synchronization codes into the video input signal, (iii) a plurality of first values and a first digital sum value both for the primary frame and (iv) a plurality of second values and a second digital sum value both for the secondary frame. A second step of the method generally comprises (B) during a second modulation pass, generating a video output signal presented from the modulation circuit by modulating the video input signal using one set of (i) the first values and (ii) the second values as determined by the first digital sum value relative to the second digital sum value.

DVD EFM modulation architecture using two passes to reduce circuit size

An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.

A method for generating syndromes for a data block is disclosed. The method generally includes the steps of (A) calculating a plurality of row syndromes and a plurality of column syndromes for the data block arranged as a Reed-Solomon product code, (B) storing only the row syndromes and the column syndromes in a local memory, (C) in an alternating sequence (i)(a) decoding the column syndromes to generate column correction results and (b) updating the row syndromes in response to the column correction results and (ii)(a) decoding the row syndromes to generate row correction results and (b) updating the column syndromes in response to the row correction results.

Delta syndrome based iterative Reed-Solomon product code decoder

An apparatus comprising a first stage and a second stage. The first stage may have a first plurality of states connected by a first topology. The second stage may have a second plurality of states connected by a second topology. The second topology may be different from the first topology.

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San Jose, CA, United States of America

Rajesh Juluri