International Business Machines Corporation

Motorola Corporation

Rajesh Bhikubhai Patel

Soummya Mallick

Romesh Mangho Jessani

Albert John Loper

A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

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Austin, TX, United States of America

Rajesh Bhikubhai Patel