Stmicroelectronics Pvt. Ltd.

Rajesh Bajaj

Anil Yadav

Sanjeev Kumar Jain

Nipun Padha

The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.

Flip chip device having simplified routing

An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree. 'This enables the PLL to maintain the proper phase even during a sleep mode of operation.'

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Greater Noida, India

Rajesh Bajaj