Freescale Semiconductor,inc.

Oracle International Corporation

Rajendran Panda

David Theodore Blaauw

Vladimir P Zolotov

Chanhee Oh

Murat R Becer

Min Zhao

Ilan Algor

Ravindraraj Ramaraju

Rajat Chaudhry

Savithri Sundareswaran

Duo Ding

Tong Xiao

Abhijit Dharchoudhury

Amir Grinshpon

Rafi Levy

Supamas Sirichotiyakul

Timothy J Edwards

Wonjoon Choi

Xiaomi Mao

Judah L Adelman

Ashutosh Chakraborty

David Moshe

Sergey V Gavrilov

Alexey L Glebov

Ruiming Li

Yury B Egorov

Dmitry Y Nadexhin

Ted Hong

A method for the simulation of a circuit is disclosed. The method may include the determination of parasitic circuit elements, and the determination of one or more operational parameters dependent upon at least the parasitic circuit elements. A model of the parasitic circuit elements may then be generated based upon the one or more operational parameters. The circuit may then be simulated using the model of the parasitic circuit elements to determine a performance level of the circuit. At least one active circuit element may be modified in response to determining that the performance level does not meet a goal.

Method for estimation of delays and slews during circuit optimization

Implementations of the present disclosure involve a system and/or method for minimum cost cycle removal from a directed graph. The system determines if a provided graph contains any cycles by assigning each vertex an integer value and comparing the integer values of vertices connected by an edge. When the value of a starting vertex is greater than an ending vertex, a cycle is present. The system then determines which edges may be removed in order to minimize the cost of breaking the cycle. The system generates a linear cost function that is equal to the sum of a cost to remove an edge multiplied by a corresponding binary variable. Constraints are generated to ensure that the result does not have any cycles. The system then solves for the minimum of the linear cost function by utilizing the constraints. The value of the binary variables may then be used to determine which edges to remove.

Method and apparatus for minimum cost cycle removal from a directed graph

A semiconductor power network () decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires ()) to be made to the network (). Voltage constraints, available white space and other constraints determine the amount of decap to be added. Wire enhancements and/or added decap can be distributed throughout a violation region () of the semiconductor circuit () design to reduce dynamic supply voltage noise so that dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level ().

On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noise

A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network nodes of a semiconductor circuit design. Voltage constraints on the decap to be added are taken into consideration such that the decap can be distributed throughout a hot spot region of the semiconductor circuit design and not be limited to placement at a single location in the circuit. Dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level.

Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noise

Processes and systems () for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise () and path based delay noise () analysis. Effective delta delay determines an impact () on victim timing of an action by aggressors that occur during a region () where victim and aggressor timing windows overlap and determines an effective delta delaycorresponding to any portionof the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty () in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time, i.e. during a switching time window (ato a+u) () when uncertainty is included.

Pessimism reduction in crosstalk noise aware static timing analysis

A method of improving performance of a dual Vintegrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.

Methods for analyzing integrated circuits and apparatus therefor

A fast transient simulator of SOI MOS circuits uses fast and accurate SOI transistor table models. The simulator uses a representation of a circuit with partitions. Each of partitions is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage, the simulator implements a transformation and uses body charge as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.

Fast simulation of circuitry having SOI transistors

A method for designing and routing circuitry having reduced cross talk. Early noise analysis () is performed after global routing () but before detailed routing () in order to repair problems () before detailed routing () is performed. In one embodiment, the early noise analysis () is preceded by probabilistic extraction (). In one embodiment, probabilistic extraction () includes determining a probability of occurrence for each configuration in a predetermined set of configurations (). Probabilistic capacitance extraction is then performed (). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (). In one embodiment, probabilistic extraction () includes estimating aggressor strength () using the probabilistic distributed coupled RC network.

Noise analysis for an integrated circuit model

The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.

Method and apparatus for controlling current demand in an integrated circuit

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Round Rock, TX, United States of America

Rajendran Panda