Intel Corporation

Other

Inter Corporation

Rajendran Nair

Stephen R Mooney

Vivek K De

Siva G Narendra

Tanay Karnik

Aaron K Martin

David GenLong Chow

Joseph T Kennedy

Nitin Y Borkar

Gregory E Dermer

Michael Pang-Cheng Hsu

Chantal E Wright

Henning Braunisch

Morteza Cyrus Afghahi

Ali Keshavarzi

Shan X Wang

Gilroy J Vandentop

Mark A Beiley

John Tang

Ankur Mohan Crawford

James T Kao

An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.

Integrated inductor structure and method of fabrication

Novel shielded flat wire pair and cable implement flat, smooth conductors coated with insulation bonded together, providing rectangular cross-sections and equidistant, smooth surfaces for high frequency signal current flow. Flat wire pairs with conductive covers and symmetrically placed shield conductors in grooves between flat wires minimize intra-pair signal flow skew. Shielded flat wire pairs are placed within a cable assembly with adjacent wire pairs oriented orthogonally, minimizing crosstalk and rendering crosstalk common-mode. Such orientation of flat wire pairs is assisted by an internal separator, which may be electrically conductive and grounded providing enhanced pair to pair isolation. Presence of flat wire pairs and an internal separator in a cable positions additional single wires in the cable firmly against a grounded external shield, ensuring a predetermined impedance for these signal wires. Shielded flat wire pairs and cables of low metal content extend electrical signaling to the millimeter wave regimes.

Flat wire shielded pair and cable

A novel flat-wire-pair and cable architecture are disclosed. The invention implements flattened conducting wires coated with insulation that are bonded to each other, providing approximately rectangular cross-sections and flat surfaces for the transport of charge through the wires. Flat wire pairs are then placed within a cable assembly such that adjacent wire pairs are oriented orthogonally or in other such manner adjacent to each other to minimize crosstalk and render crosstalk common-mode. Flat wire pairs are also shielded for additional cross-talk minimization as well as near-field EMI minimization. A cable consisting of multiple flat wire pairs may also be shielded in its external jacket that maintains cable structure, and may include additional conductors for reference and static signals. Through these enhancements, the invention cable architecture eliminates intra-pair and inter-pair skew while substantially reducing signal loss due to skin-effect as well as rendering crosstalk harmless. Shielded flat wire pair cables are thus ideally suited to very high-speed data communication over significant distances.

Shielded flat pair cable architecture

A device comprises a substrate core having power paths through it and an input/output signal routing layer upon the core substrate. An integrated circuit may be arranged on the routing layer such that the integrated circuit is electrically coupled to the substrate core through the routing layer.

Decoupled signal-power substrate architecture

The invention proposes noise suppression circuits that are assembled together with capacitors on a CPU package. Charge is conveyed from the capacitors dedicated to the active noise suppression function through electrical circuit pathways such as controlled electronic switches integrated into a semiconductor substrate. These circuit pathways connect to the capacitor terminals through the package of the active noise suppression semiconductor chip. The circuits within the active device may be any combination of semiconductor switches and/or voltage regulators, and may also contain voltage and current sensing circuitry. The charge transfer switches are designed with control circuitry that dynamically modulate the turn-on threshold voltage of the switches and maintain the switches at an operating point very close to actual turn-on. These enhancements ensure very fast turn-on action for the switches improving voltage droop suppression capability.

Voltage droop suppressing circuit

A novel push-pull differential signaling circuit architecture exceptionally suited for 2-wire transceiver implementations is disclosed. The invention Class-B differential signaling (CBDS) architecture fully utilizes equivalent current sources connecting from the positive power rail and to the negative power rail to generate a 'true-differential' signal in a differential interconnect pair. By adopting a 'Class B' or push-pull drive structure, the invention architecture maximizes power efficiency, improving upon traditional differential signaling implementations by a factor of 2 or more. A novel combination of a bias circuit and the Class B output drive circuit ensures that the push and pull currents are very closely matched over fabrication process, voltage and temperature. The current mode operation and bi-lateral nature of the output driver ensures that there are no current spikes in the power supply connecting to the invention circuits, thereby minimizing on-chip decoupling capacitance requirements. Due to the symmetry in the push and pull current action, EM emissions from the external interconnect pair is greatly reduced, allowing much higher current drive (14 mA) and correspondingly higher voltage swings.

Push pull high-swing capable differential signaling circuits

The invention proposes an interposer assembly architecture for noise suppression circuits on the package of a CPU or high power, high frequency VLSI device. In this architecture, charge is stored on dedicated capacitors at a voltage substantially higher than the operating voltage of the VLSI device. These capacitors are mounted upon active circuits that are packaged to match the size and form factor of the capacitors and this assembly is then attached to the package substrate. Charge is conveyed from the capacitor terminals on the backside of the packaged active circuits chip. Depending upon the capacitor construction, these terminals may either be double-sided contact terminals along the edge of the active device's package, or may be feed-through contacts. The active device attaches to the package substrate through both edge terminals and terminals built-up on the surface of the chip, increasing it's number of electrical pathways into the package substrate, matching the package substrate interconnect and reducing the electrical impedance of the charge flow path. The circuits within the active device may be any combination of semiconductor switches and/or voltage regulators, and may also contain voltage and current sensing circuitry.

Voltage droop suppressing active interposer

An adaptable, low-power drive circuit for transistor switches requiring control input current is disclosed. In one embodiment of the invention, a current source output replaces the prior art voltage drive circuits and associated external current-limiting resistor. The current-source drive circuit provides both a high impedance as well as variability. The high impedance of the current-source drive circuit enables a reduction in the value of the resistance-bypass capacitor employed in the prior art. The variability in the output current provided by the current-source circuit allows the drive circuits to optimize the control current flowing into the switch device as the characteristics of the switch device change with operating temperature. The drive circuit is capable of providing as output either a desired current, at a high output impedance, or a desired voltage, at a low output impedance, employing a shared amplifier and output transistor. The drive circuit also derives current from the much lower output voltage of the buck conversion system that the invention is used in. This minimizes the static power dissipated in driving the switch, and also minimizes the energy expenditure incurred in increasing the output current to modulate the power switch resistance that increases with increasing temperature.

Method and apparatus for driving low input impedance power transistor switches

A high capacitance substrate. The substrate includes a core tolerant to sintering thereon of a high k material to provide increased capacitance. The core may be non-ceramic. The material sintered thereon may have a dielectric constant in excess of about 4. The substrate may be a package substrate electrically coupled to a die.

High capacitance package substrate

A circuit including a signal input to receive a signal, a buffer circuit to receive the input signal and to generate a buffer circuit output, and a voltage following circuit to receive the signal input and to generate a voltage following output. The buffer circuit output and the voltage following circuit output are coupled to a circuit output node.

Symmetric voltage follower buffer

A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.

Method and apparatus for weak inversion mode MOS decoupling capacitor

In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n&plus; gate poly and n&plus; source/drain regions in an n-body; p&plus; gate poly and n&plus; source/drain regions in an n-body; p&plus; gate poly and p&plus; source/drain regions in an n-body; p&plus; gate poly and p&plus; source/drain regions in a p-body; n&plus; gate poly and p&plus; source/drain regions in a p-body; n&plus; gate poly and n&plus; source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.

Decoupling capacitors for thin gate oxides

A phase lock loop circuit including a voltage controlled oscillator and a phase detector having a sampling circuit and a linear voltage-to-current converter to create a control voltage for the voltage controlled oscillator. The phase lock loop circuit comprising a voltage-to-current circuit to influence a voltage on a capacitor, the voltage controlled oscillator responsive to the voltage on the capacitor, and the sampling circuit responsive to the first and second clock signals to generate two voltage values.

Phase lock loop apparatus

A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

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Hillsboro, OR, United States of America

Rajendran Nair