Intel Corporation

Microsoft Technology Licensing, LLC

Rajendra S Yavatkar

Tsung-Yuan Charles Tai

Christian Maciocco

Richard A Uhlig

Jeffrey R Jackson

Ashok Sunder Rajan

Daniel J Dahle

David M Durham

Lakshman Krishnamurthy

Russell Jerome Fenger

Sanjay Bakshi

Steve Adams

Ravi L Sahita

Muthaiah Venkatachalam

Vedvyas Shanbhogue

John R Douceur

Ren Wang

Michael E Kounavis

Ioannis T Schoinas

Sankaran M Menon

David M Putzolu

Yoram Bernet

Michael J Espig

Ramana V Rachakonda

Ofer Bar

James E Toga

Sridhar Valluru

Makaram Raghunandan

Shou C Chen

Dylan C Larson

Dave Edwards

Carol Ann Bell

Eyal Dolev

Carlos Abad Vazquez

Elena Chaikovsky

Geoffrey R Gustafson

Steven Adams

In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.

Cross-function virtualization of a telecom core network

A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data.

Apparatus, system and method for a common unified debug architecture for integrated circuits and SoCs

Apparatuses and methods for page coloring to associate memory pages with programs are disclosed. In one embodiment, an apparatus includes a paging unit and an interface to access a memory. The paging unit includes translation logic and comparison logic. The translation logic is to translate a first address to a second address. The first address is to be provided by an instruction stored in a first page in the memory. The translation is based on an entry in a data structure, and the entry is to include a base address of a second page in the memory including the second address. The comparison logic is to compare the color of the first page to the color of the second page. The color of the first page is to indicate association of the first page with a first program including the first instruction. The data structure entry is also to include the color of the second page to indicate association of the second page with the first program or a second program.

Page coloring to associate memory pages with programs

Systems and methods may provide for determining a skin tone distribution for a plurality of pixels in a video signal and using the skin tone distribution to conduct one or more blob-based hand gesture determinations with respect to the video signal. In one example, the video signal includes two-dimensional (2D) image data, and the skin tone distribution has an execution time budget that is greater than an execution time budget of the blob-based hand gesture determinations.

Performing hand gesture recognition using 2D image data

A method and apparatus to route information over a network is described.

Method and apparatus to perform network routing

An embodiment may include network controller to be comprised in a first node. The node may be communicatively coupled to a network and may include a host processor to execute an operating system environment. The operating system environment may include, at least in part, a communication protocol stack and an application. The circuitry may receive, at least in part, a packet from the network. The packet may include, at least in part, a header and payload. At least one portion of the payload may be associated with the application. The circuitry may issue at least one portion of the header to the stack. The circuitry may issue the at least one portion of the payload to a destination device in a manner that by-passes involvement of the stack. The destination device may be specified, at least in part, by the application. Many alternatives, variations, and modifications are possible.

Network controller circuitry to issue at least one portion of packet payload to device in manner that by-passes communication protocol stack involvement

A border gateway has a control card and at least one line card. The control card has a control processor to execute a control portion of an exterior gateway protocol and a routing table of exterior gateway routes and devices. The line card has a line processor to execute an offload portion of an exterior gateway protocol and a communications port to allow termination of at least one communication link. A backplane allows the control card and the line card to communicate.

Distributed exterior gateway protocol

A method and apparatus to insert control blocks into a stream of data user blocks. Data user blocks are transmitted onto a network during transmission slots. One of the data user blocks is buffered during one of the transmission slots. Instead of transmitting the buffered data user block during this transmission slot, a control block is transmitted onto the network in the data user block's place. Transmission of the data user block is delayed until the next transmission slot. The control block is inserted at a required position into the stream of data user blocks at a transmit engine, as opposed to a queue manager, leaving the queue manager unconcerned with the insertion details of the control block. Insertion of the control block by the transmit engine enables the queue manager to handle frames containing large numbers of user blocks as a single unit (e.g., such as is the case with AAL-5) and avoid complications related to inserting the control block in the midst of these frames.

Method and apparatus to implement operation and maintenance (OAM) functions on a network processor

According to some embodiments, execution information is received from a first development tool. Execution information is also received from a second development tool. Based on the first execution information and the second execution information, operation of the first development tool may be controlled. According to some embodiments, the first and second development tools are associated with different processor architectures.

System development tool

A method and apparatus of implementing protocol state machines that conserve energy on energy conscious devices is disclosed. Under this method, most of the energy consuming protocol state machine context invocations or operations are aggregated in time and are scheduled at regular intervals. Such an aggregation leads to many contexts executing concurrently in a burst prior to entering a dormant state. Thus, resource usage can reach a predictable rate pattern of idle and active cycles. With such a pattern, it is possible to take advantage of the energy saving features of processors by downshifting the processor clock speed and use of other resources such as peripherals and buses. The intervals are configured to achieve a tradeoff between timely execution and energy consumption. The aggregation operates across two dimensions, namely, multiple instances of a protocol state machine and multiple layers of protocols in a layered architecture.

Method and apparatus for managing energy usage of processors while executing protocol state machines

A multi-media call application is disclosed. The application guarantees quality of service (QOS) for a packet based multi-media call (CALL). The guaranty is effectuated through call associated individual media stream bandwidth control.

Ensuring quality of service (QOS) for a multi-media calls through call associated individual media stream bandwidth control

Growing community of inventors

Portland, OR, United States of America

Rajendra S Yavatkar