Western Digital Technologies, Inc.

Rajendra Prasad Mishra

Ajith Kumar Battaje

Tanay Goel

Kenneth Alan Okin

Ashish Singhai

Sandeep Sharma

George Moussa

Krishanth Skandakumaran

Sriram Rupanagunta

Srikant Sadasivam

A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request for garbage collection, identify a range of physical blocks in a storage device, query a bitmap, the bitmap having a bit for each physical block in the range of physical blocks, determine a status associated with a first bit from the bitmap, in response to determining the status associated with the first bit is a first state, add a first physical block associated with the first bit to a list of physical blocks for relocation, and relocate the list of physical blocks.

Translation lookup and garbage collection optimizations on storage system with paged translation table

A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive in a memory, a first logical block entry for a first dump group and a second logical block entry for a second dump group; store in a reverse translation table, the first logical block entry for the first dump group and the second logical block entry for the second dump group; determine a first sequence number associated with the stored first logical block entry and the stored second logical block entry in the reverse translation table, wherein the first sequence number is a snapshot marker that determines a timestamp associated with the first logical block and the second logical block; and persist the first logical block entry for the first dump group in the storage device.

Incremental snapshot based technique on paged translation systems

A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request to select translation table entries to store in a storage device, determine a plurality of translation table entries associated with a dump unit, allocate the plurality of translation table entries into a first group of translation table entries associated with a first node and a second group of translation table entries associated with a second node, the first group of translation table entries being frequently accessed and the second group of translation table entries being rarely accessed. determine a first status associated with a first recent access bit for a first translation table entry, the first translation table entry being included in the first group of translation table entries, and add the first translation table entry to the second group of translation table entries.

Efficient management of paged translation maps in memory and flash

A system comprising a processor and a memory storing instructions that, when executed, cause the system to identify a plurality of dump units associated with a translation table in a storage device, determine a plurality of snapshot markers associated with the plurality of dump units, calculate a first value of a first snapshot marker from the plurality of snapshot markers in the storage device, identify a second snapshot marker from an additional source, the second snapshot marker having a second value satisfying the first value, retrieve a dump unit associated with the second snapshot marker from the additional source, and reconstruct the translation table using the dump unit.

Embodiments of the present invention receive I/O commands expressed in either vendor-specific or non-vendor-specific protocols and normalize them into a common format for execution by different memory devices. Embodiments of the present invention identify these I/O commands using parameters common to both types of protocols. In this fashion, embodiments store normalized commands in data structures for execution by memory devices in which the normalized commands represent instructions for performing an action corresponding with execution of the original I/O command. Accordingly, embodiments of the present invention save resources with respect to hardware and software maintenance costs.

Method and system for a common processing framework for memory device controllers

Embodiments of the present invention are operable to efficiently schedule memory device commands, such as flash memory device commands, while taking into account the interdependencies of processing such commands. As such embodiments of the present invention order commands to make sure that data is written and read from memory devices in a coherent fashion using command groups. Commands within such command groups are scheduled concurrently or in parallel. In this fashion, embodiments of the present invention promote efficient execution of memory device commands while maintaining any required arbitrary ordering requirements.

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Santa Clara, CA, United States of America

Rajendra Prasad Mishra