Intel Corporation

Rajendra M Abhyankar

Erik De La Iglesia

Pochang Hsu

Siripong Sritanyaratana

John William Horigan

The present invention relates to an error correction and selective inversion circuit (ESIC). The ESIC includes a power-on logic state (POLS) bus having a data signal and an error code correction (ECC) generator having an input coupled to the POLS bus. The ECC generator includes one or more correction pins. The ESIC also includes an inversion generator having an input attached to the POLS bus in parallel with the ECC generator. The output of the inversion generator is integrated with the output of on or more correction pins from the ECC generator so as to form an inverted data signal output. An inverted data signal is recovered by the ESIC in an inversion recovery.

Bus power savings using selective inversion in an ECC system

In some embodiments, the invention includes a system having a normal operating mode and a suspend mode. The system includes event recognition circuitry to provide an event status signal. The system also includes clock generating circuitry with selective stretching capability to generate an internal clock signal and to receive the event status signal, and wherein when the event status signal has a first logic state, the clock generating circuitry stretches the internal clock signal by a number of phases per cycle of a bus clock signal wherein an alignment relationship between the internal clock signal and the bus clock signal is immediately deterministic in transitions between the suspend mode and the normal operating mode.

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Santa Clara, CA, United States of America

Rajendra M Abhyankar