Nvidia Corporation

Rajendra Kumar reddyS

Amit D Sanghani

Shantanu Sarangi

Milind Bhaiyyasaheb Sonawane

Jonathon E Colburn

Bala Tarun Nelapatla

Sailendra Chadalavada

Sailendra Chadalavda

In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

Granular dynamic test systems and methods

A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.

Scan system interface (SSI) module

Growing community of inventors

Bengaluru, India

Rajendra Kumar reddyS