Stats Chippac Pte. Ltd.

Chippac, Inc.

Meta Platforms Technologies, LLC

Hewlett-packard Company

Facebook Technologies, LLC

Other

Agilent Technologies, Inc.

Rajendra D Pendse

KyungOe Kim

TaeWoo Kang

Kyung-Moon Kim

Nazir Ahmad

Yaojian Lin

Pandi Chelvam Marimuthu

Young-Do Kweon

Reza A Pagaila

Byung Joon Han

Hun-Teak Lee

Ki-Youn Jang

Jong-Kook Kim

Chul-Sik Kim

Il Kwon Shim

Samuel Waising Tam

Byung Tai Do

Linda Pei Ee Chua

Marcos Karnezos

Won Kyoung Choi

Jun Mo Koo

Youngcheol Kim

Shuangwu Huang

Kenneth D Scholz

Farid Matta

TaeKeun Lee

Kevin C Douglas

Brahram Afshari

GuiChea Na

GwangJin Kim

Seng Guan Chow

Kang Chen

Jianmin Fang

HunTeak Lee

Flynn P Carson

Chien Ouyang

Hun Teak Lee

Koo Hong Lee

Taewoo Kang

Kyung Moon Kim

Mukul Joshi

Andrea Y Chen

Haengcheol Choi

Orion K Starr

Moon Hee Lee

Walter A Bush, Jr

Young Do Kweon

Rita Horner

Jaime L Del Campo

An article including a semiconductor die including integrated circuitry is described. The semiconductor die defines a first major surface, a second major surface opposite the first major surface, and a plurality of perimeter walls joining the first major surface and the second major surface. The article further includes at least one through silicon via extending through the semiconductor die between the first major surface and the second major surface and a fill material surrounding at least part of the semiconductor die. The fill material contacts at least one of the plurality of perimeter walls, and a surface of the fill material is substantially co-planar with the first major surface of the semiconductor die. The article further includes at least one redistribution layer on the first major surface of the semiconductor die and the surface of the fill material.

Semiconductor reconstitution

Systems and devices describe an augmented-reality glasses having a plurality of panels of light emitters arranged to form an array of light emitters, collimation optics for collimating light received from the array of light emitters, an optical coupler for receiving the collimated light, and a waveguide for display of augmented-reality content to a wearer of the augmented-reality glasses. In some embodiments, the array of light emitters includes light emitters generating three colors, each panel of the plurality of panels of light emitters having light emitters generating a same color, and each panel of the plurality of panels of light emitters positioned on a surface of a semiconductor with at least one integrated circuit. The array of light emitters can be two-dimensional array of light emitters arranged on a common plane and characterized by a pitch that is less than 2 μm.

Display projector systems and devices for augmented-reality

In some examples, an article comprises a semiconductor including at least one integrated circuit, a μLED array on a first surface of the semiconductor, and a fill material disposed on a first edge of the semiconductor. The first edge of the μLED array or the semiconductor is oriented substantially perpendicular to the first surface of the semiconductor.

Integrating control circuits with light emissive circuits with dissimilar wafer sizes

Disclosed herein is an LED device that includes a display package and a plurality of LED dies arranged on a top surface of the display package. The display package includes a molding compound, a backplane die, and at least one spacer structure, with the backplane die and the at least one spacer structure being embedded within the molding compound. In some embodiments, the plurality of LED dies includes a first die containing red LEDs, a second die containing green LEDs, and a third die containing blue LEDs. The backplane die includes driver circuits configured to drive LEDs in the plurality of LED dies, for example, LEDs of the first die, the second die, and the third die. The at least one spacer structure has a higher thermal conductivity than the molding compound and is configured to dissipate heat generated by the LEDs in the plurality of LED dies.

Managing thermal resistance and planarity of a display package

Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.

Artificial reality system having system-on-a-chip (soc) integrated circuit components including stacked sram

In some examples, an article comprises a semiconductor including at least one integrated circuit and an inorganic semiconductor layer bonded to a first surface of the semiconductor. The inorganic semiconductor layer comprises a &#x3bc;LED array, and the first surface of the semiconductor extends beyond a first edge of the inorganic semiconductor layer. The first edge of the inorganic semiconductor layer is oriented substantially perpendicular to the first surface of the semiconductor.

Disclosed herein are techniques for aligning a collimator assembly with an array of LEDs and apparatuses formed using the disclosed techniques. According to certain embodiments, a display projector includes a display device and a collimator assembly. The display device includes a backplane including a first plurality of features. The display device further includes a plurality of dies. Each die of the plurality of dies comprises a plurality of light emitting diodes and is bonded to the backplane. The collimator assembly includes a plurality of lenses and a second plurality of features. The collimator assembly is attached to the display device through coupling the first plurality of features with the second plurality of features such that the plurality of dies are aligned with the plurality of lenses.

Aligning a collimator assembly with LED arrays

Artificial reality system having system-on-a-chip (SoC) integrated circuit components including stacked SRAM

An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.

Integrated display devices

Disclosed herein are display devices having a left projector and a right projector. According to certain embodiments, a display device includes a first display package having a first LED die, a second LED die, a third LED die, and a first backplane die that is electrically connected to the first LED die, the second LED die, and the third LED die. Each of the first LED die, the second LED die, and the third LED die is symmetric about a first plane that is parallel to an emission direction of the first LED die and perpendicular to a longitudinal direction of the first LED die. The first backplane die is symmetric about a second plane that is parallel to the emission direction of the first LED die and parallel to the longitudinal direction of the first LED die.

Left and right projectors for display device

Disclosed herein are techniques for managing the thermal resistance and the planarity of a display package. According to certain embodiments, a device includes a display package having a molding compound; a plurality of light emitting diode (LED) dies arranged on a top surface of the display package, wherein each LED die of the plurality of LED dies includes a plurality of LEDs; a backplane die embedded within the molding compound of the display package, wherein the backplane die is electrically coupled to each LED die of the plurality of LED dies; and at least one spacer structure embedded within the molding compound of the display package. The backplane die and the at least one spacer structure together provide mechanical support and planar alignment for the plurality of LED dies arranged on the top surface of the display package. The at least one spacer structure has a first thermal conductivity, and the molding compound has a second thermal conductivity lower than the first thermal conductivity.

Disclosed herein are techniques for aligning a collimator assembly with an array of LEDs. According to certain embodiments, a method includes using lithography to form a first plurality of contact pads and a second plurality of contact pads on a backplane; bonding a plurality of dies to the first plurality of contact pads, wherein each of the plurality of dies comprises a plurality of light emitting diodes; forming a first plurality of features on the second plurality of contact pads; and aligning a plurality of lenses on an assembly with the plurality of dies by coupling a second plurality of features on the assembly with the first plurality of features on the second plurality of contact pads.

A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.

Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration

An IC chip comprises LED devices exposed on a front side of the IC chip, I/O bumps on a back side of the IC chip, a first die forming a stack with the LED devices and comprising driver circuits electrically connected to the LED devices, a first circuit that extends along the vertical direction from the front side of the IC chip towards a back side of the IC chip and across at least a thickness of the first die to provide electrical connections between the LED devices and at least some of the I/O bumps, a second die including pipelining circuits and control circuits for the driver circuits, a second circuit that extends from the second die, and a circuit board electrically connected to the I/O bumps and to a power system.

An assembly of circuit dies is stacked through oxide-oxide bonding. The assembly includes a silicon substrate, in which a plurality of through-silicon-vias are formed. The silicon substrate is attached onto a die through dielectric-dielectric bonding with at least part of the through-silicon-vias electrically connected to the die. The silicon substrate and die are attached onto another die through oxide-oxide bonding. Then the through-silicon-vias are revealed. The silicon substrate functions as a carrier substrate before the revealing. The silicon substrate and two dies can be attached to a printed circuit board, which is electrically connected to the two dies. One or more electrical components can be attached onto the silicon substrate and electrically connected to the die through the through-silicon-vias. The silicon substrate may include a metal element for diffusing heat generated from operation of the one or more electrical components.

Stacking of three-dimensional circuits including through-silicon-vias

Growing community of inventors

Fremont, CA, United States of America

Rajendra D Pendse