National Semiconductor Corporation

Rajeeva Lahri

Ali A Iranmanesh

Christopher S Blair

Rick C Jerome

Vida Ilderem

Alan G Solheim

Madan Biswal

George E Ganschow

Bamdad Bastani

Bancherd DeLong

James L Bouknight

Steve M Leibiger

Tad Davies

A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Method of fabricating BiCMOS device

A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wraparound silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

Reducing base resistance of a BJT by forming a self aligned silicide in

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Puyallup, WA, United States of America

Rajeeva Lahri